[Skiboot] [PATCH 3/5] npu2: MCD refactor
Michael Neuling
mikey at neuling.org
Mon Nov 13 22:06:42 AEDT 2017
Pull out MCD writing code into npu2_mcd_init()
No functional change.
Signed-off-by: Michael Neuling <mikey at neuling.org>
---
hw/npu2.c | 33 ++++++++++++++++++++-------------
1 file changed, 20 insertions(+), 13 deletions(-)
diff --git a/hw/npu2.c b/hw/npu2.c
index 9f2aaad45e..79ebaff75f 100644
--- a/hw/npu2.c
+++ b/hw/npu2.c
@@ -849,21 +849,10 @@ static void npu2_write_mcd(struct npu2 *p, uint64_t pcb_addr, uint64_t addr,
xscom_write(p->chip_id, pcb_addr, val);
}
-static void npu2_hw_init(struct npu2 *p)
+static void npu2_mcd_init(struct npu2 *p)
{
int i;
- uint64_t val, size, addr, gpu_min_addr, gpu_max_addr, total_size;
-
- npu2_ioda_reset(&p->phb, false);
-
- /* Enable XTS retry mode */
- val = npu2_read(p, NPU2_XTS_CFG);
- npu2_write(p, NPU2_XTS_CFG, val | NPU2_XTS_CFG_MMIOSD | NPU2_XTS_CFG_TRY_ATR_RO);
-
- if (!is_p9dd1()) {
- val = npu2_read(p, NPU2_XTS_CFG2);
- npu2_write(p, NPU2_XTS_CFG2, val | NPU2_XTS_CFG2_NO_FLUSH_ENA);
- }
+ uint64_t size, addr, gpu_min_addr, gpu_max_addr, total_size;
/* Init memory cache directory (MCD) registers. */
phys_map_get(p->chip_id, GPU_MEM, NPU2_LINKS_PER_CHIP - 1,
@@ -901,6 +890,24 @@ static void npu2_hw_init(struct npu2 *p)
}
}
+static void npu2_hw_init(struct npu2 *p)
+{
+ uint64_t val;
+
+ npu2_ioda_reset(&p->phb, false);
+
+ /* Enable XTS retry mode */
+ val = npu2_read(p, NPU2_XTS_CFG);
+ npu2_write(p, NPU2_XTS_CFG, val | NPU2_XTS_CFG_MMIOSD | NPU2_XTS_CFG_TRY_ATR_RO);
+
+ if (!is_p9dd1()) {
+ val = npu2_read(p, NPU2_XTS_CFG2);
+ npu2_write(p, NPU2_XTS_CFG2, val | NPU2_XTS_CFG2_NO_FLUSH_ENA);
+ }
+
+ npu2_mcd_init(p);
+}
+
static int64_t npu2_map_pe_dma_window_real(struct phb *phb,
uint64_t pe_num,
uint16_t window_id,
--
2.14.1
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