[Skiboot] [PATCH 1/5] npu2: Create npu2_write_mcd()

[Michael Neuling]

This code is replicated, so let's put it in a function. Also add some cleanups.

No functional change.

Signed-off-by: Michael Neuling <mikey at neuling.org>
---
 hw/npu2.c           | 24 ++++++++++++++++--------
 include/npu2-regs.h |  3 +++
 2 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/hw/npu2.c b/hw/npu2.c
index d215b4ce97..77b8e8c133 100644
--- a/hw/npu2.c
+++ b/hw/npu2.c
@@ -834,6 +834,20 @@ static int64_t npu2_ioda_reset(struct phb *phb, bool purge)
 	return OPAL_SUCCESS;
 }
 
+static void npu2_write_mcd(struct npu2 *p, uint64_t pcb_addr, uint64_t addr,
+			   uint64_t size)
+{
+	uint64_t val;
+
+	NPU2DBG(p, "Setting MCD addr:%llx\n", pcb_addr);
+	assert(is_pow2(size));
+
+	val = MCD_BANK_CN_VALID;
+	val = SETFIELD(MCD_BANK_CN_SIZE, val, (size >> 25) - 1);
+	val = SETFIELD(MCD_BANK_CN_ADDR, val, addr >> 25);
+	xscom_write(p->chip_id, pcb_addr, val);
+}
+
 static void npu2_hw_init(struct npu2 *p)
 {
 	int i;
@@ -873,10 +887,7 @@ static void npu2_hw_init(struct npu2 *p)
 	/* Allocate the biggest chunk first as we assume gpu_max_addr has the
 	 * highest alignment. */
 	addr = gpu_max_addr - size;
-	val = PPC_BIT(0);
-	val = SETFIELD(PPC_BITMASK(13, 29), val, (size >> 25) - 1);
-	val = SETFIELD(PPC_BITMASK(33, 63), val, addr >> 25);
-	xscom_write(p->chip_id, MCD0_BANK0_CN3, val);
+	npu2_write_mcd(p, MCD0_BANK0_CN3, addr, size);
 	total_size -= size;
 	if (total_size) {
 	/* total_size was not a power of two, but the remainder should
@@ -885,10 +896,7 @@ static void npu2_hw_init(struct npu2 *p)
 		size = 1ull << ilog2(total_size);
 		addr -= size;
 		assert(addr <= gpu_min_addr);
-		val = PPC_BIT(0);
-		val = SETFIELD(PPC_BITMASK(13, 29), val, (size >> 25) - 1);
-		val = SETFIELD(PPC_BITMASK(33, 63), val, addr >> 25);
-		xscom_write(p->chip_id, MCD1_BANK0_CN3, val);
+		npu2_write_mcd(p, MCD1_BANK0_CN3, addr, size);
 	}
 }
 
diff --git a/include/npu2-regs.h b/include/npu2-regs.h
index 307e93bd4c..c77a43a4c8 100644
--- a/include/npu2-regs.h
+++ b/include/npu2-regs.h
@@ -28,6 +28,9 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask);
  * code */
 #define MCD0_BANK0_CN3 0x301100d
 #define MCD1_BANK0_CN3 0x301140d
+#define	MCD_BANK_CN_VALID	PPC_BIT(0)
+#define	MCD_BANK_CN_SIZE	PPC_BITMASK(13,29)
+#define	MCD_BANK_CN_ADDR	PPC_BITMASK(33,63)
 
 #define NPU2_REG_OFFSET(stack, block, offset) \
 	(((stack) << 20) | ((block) << 16) | (offset))
-- 
2.14.1