[Skiboot] [PATCH] hdata/cpu: account for p9 shared caches
stewart at linux.vnet.ibm.com
Fri Mar 31 18:01:13 AEDT 2017
Oliver O'Halloran <oohall at gmail.com> writes:
> On P9 the L2 and L3 caches are shared between pairs of SMT=4 cores.
> Currently this is not accounted for when creating caches nodes in
> the device tree. This patch adds additional checking so that a
> cache node is only created for the first core in the pair and
> the second core will reference the cache correctly.
> Signed-off-by: Oliver O'Halloran <oohall at gmail.com>
Merged to master as of b265154139b59295f7f2138459606e797a12d9f5
OPAL Architect, IBM.
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