[Skiboot] [PATCH 07/14] hdat: stop using proc_int_line in favor of pir
Oliver O'Halloran
oohall at gmail.com
Thu Jan 12 14:54:06 AEDT 2017
This field has been deprecated in the P9 HDAT format. Due to how XICS
works proc_int_line has always been equal to the pir field of the same
structure. This equality has always been enforced by an assert() in skiboot
on P7 and P8 so it's safe to just look at the pir field instead.
Signed-off-by: Oliver O'Halloran <oohall at gmail.com>
---
hdata/pcia.c | 14 +++++++-------
hdata/test/p8-840-spira.dt | 12 ++++++------
hdata/test/p81-811.spira.dt | 40 ++++++++++++++++++++--------------------
3 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/hdata/pcia.c b/hdata/pcia.c
index 1c339d01c410..9b210e4dfbff 100644
--- a/hdata/pcia.c
+++ b/hdata/pcia.c
@@ -72,7 +72,7 @@ static void add_xics_icp(const void *pcia, u32 tcount, const char *compat)
t = find_tada(pcia, i);
assert(t);
if (i == 0)
- irange[0] = be32_to_cpu(t->proc_int_line);
+ irange[0] = be32_to_cpu(t->pir);
reg[i * 2] = cpu_to_be64(cleanup_addr(be64_to_cpu(t->ibase)));
reg[i * 2 + 1] = cpu_to_be64(0x1000);
}
@@ -125,8 +125,8 @@ static struct dt_node *add_core_node(struct dt_node *cpus,
>> CPU_ID_NUM_SECONDARY_THREAD_SHIFT) + 1;
assert(threads <= PCIA_MAX_THREADS);
- prlog(PR_INFO, "CORE[%i]: PIR=%i RES=%i %s %s(%u threads)\n",
- pcia_index(pcia), t->pir, t->proc_int_line,
+ prlog(PR_INFO, "CORE[%i]: PIR=%.8x %s %s(%u threads)\n",
+ pcia_index(pcia), be32_to_cpu(t->pir),
ve_flags & CPU_ID_PACA_RESERVED
? "**RESERVED**" : cpu_state(ve_flags),
be32_to_cpu(t->pir) == boot_cpu->pir ? "[boot] " : "", threads);
@@ -146,7 +146,7 @@ static struct dt_node *add_core_node(struct dt_node *cpus,
}
cpu = add_core_common(cpus, cache, timebase,
- be32_to_cpu(t->proc_int_line), okay);
+ be32_to_cpu(t->pir), okay);
/* Core attributes */
attr = HDIF_get_idata(pcia, SPPCIA_IDATA_CPU_ATTR, &size);
@@ -155,7 +155,7 @@ static struct dt_node *add_core_node(struct dt_node *cpus,
/* Add cache info */
l2_phandle = add_core_cache_info(cpus, cache,
- be32_to_cpu(t->proc_int_line), okay);
+ be32_to_cpu(t->pir), okay);
dt_add_property_cells(cpu, "l2-cache", l2_phandle);
if (proc_gen == proc_gen_p7)
@@ -176,8 +176,8 @@ static struct dt_node *add_core_node(struct dt_node *cpus,
threads = i;
break;
}
- iserv[i] = t->proc_int_line;
- assert(t->proc_int_line == t->pir);
+
+ iserv[i] = t->pir;
}
dt_add_property(cpu, "ibm,ppc-interrupt-server#s", iserv, 4 * threads);
diff --git a/hdata/test/p8-840-spira.dt b/hdata/test/p8-840-spira.dt
index f538d2289f70..b71388973907 100644
--- a/hdata/test/p8-840-spira.dt
+++ b/hdata/test/p8-840-spira.dt
@@ -1,22 +1,22 @@
SPIRA-S found.
Got PCIA !
CORE[0]: HW_PROC_ID=1 PROC_CHIP_ID=0 EC=0x21 OK
-CORE[0]: PIR=671088640 RES=671088640 OK (8 threads)
+CORE[0]: PIR=00000028 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[1]: HW_PROC_ID=3 PROC_CHIP_ID=0 EC=0x21 OK
-CORE[1]: PIR=1610612736 RES=1610612736 OK (8 threads)
+CORE[1]: PIR=00000060 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[2]: HW_PROC_ID=4 PROC_CHIP_ID=0 EC=0x21 OK
-CORE[2]: PIR=1744830464 RES=1744830464 OK (8 threads)
+CORE[2]: PIR=00000068 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[3]: HW_PROC_ID=8 PROC_CHIP_ID=1 EC=0x21 OK
-CORE[3]: PIR=-1342177280 RES=-1342177280 OK (8 threads)
+CORE[3]: PIR=000000b0 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[4]: HW_PROC_ID=10 PROC_CHIP_ID=1 EC=0x21 OK
-CORE[4]: PIR=-402653184 RES=-402653184 OK (8 threads)
+CORE[4]: PIR=000000e8 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[5]: HW_PROC_ID=11 PROC_CHIP_ID=1 EC=0x21 OK
-CORE[5]: PIR=-268435456 RES=-268435456 OK (8 threads)
+CORE[5]: PIR=000000f0 OK (8 threads)
Cache: I=32 D=64/512/8192/0
IPLPARAMS: 1 serial ports in array
IPLPARAMS: Serial 0 rsrc: 2a00 loc: U78C9.001.WZS0CWX-P1-C1-T1
diff --git a/hdata/test/p81-811.spira.dt b/hdata/test/p81-811.spira.dt
index 2286915481e0..e8ec6f463829 100644
--- a/hdata/test/p81-811.spira.dt
+++ b/hdata/test/p81-811.spira.dt
@@ -1,63 +1,63 @@
Got PCIA !
CORE[0]: HW_PROC_ID=0 PROC_CHIP_ID=0 EC=0x21 OK
-CORE[0]: PIR=536870912 RES=536870912 OK (8 threads)
+CORE[0]: PIR=00000020 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[1]: HW_PROC_ID=2 PROC_CHIP_ID=0 EC=0x21 OK
-CORE[1]: PIR=805306368 RES=805306368 OK (8 threads)
+CORE[1]: PIR=00000030 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[2]: HW_PROC_ID=3 PROC_CHIP_ID=0 EC=0x21 OK
-CORE[2]: PIR=1610612736 RES=1610612736 OK (8 threads)
+CORE[2]: PIR=00000060 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[3]: HW_PROC_ID=4 PROC_CHIP_ID=0 EC=0x21 OK
-CORE[3]: PIR=1744830464 RES=1744830464 OK (8 threads)
+CORE[3]: PIR=00000068 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[4]: HW_PROC_ID=5 PROC_CHIP_ID=0 EC=0x21 OK
-CORE[4]: PIR=1879048192 RES=1879048192 OK (8 threads)
+CORE[4]: PIR=00000070 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[5]: HW_PROC_ID=7 PROC_CHIP_ID=1 EC=0x21 OK
-CORE[5]: PIR=-1476395008 RES=-1476395008 OK (8 threads)
+CORE[5]: PIR=000000a8 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[6]: HW_PROC_ID=8 PROC_CHIP_ID=1 EC=0x21 OK
-CORE[6]: PIR=-1342177280 RES=-1342177280 OK (8 threads)
+CORE[6]: PIR=000000b0 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[7]: HW_PROC_ID=9 PROC_CHIP_ID=1 EC=0x21 OK
-CORE[7]: PIR=-536870912 RES=-536870912 OK (8 threads)
+CORE[7]: PIR=000000e0 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[8]: HW_PROC_ID=10 PROC_CHIP_ID=1 EC=0x21 OK
-CORE[8]: PIR=-402653184 RES=-402653184 OK (8 threads)
+CORE[8]: PIR=000000e8 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[9]: HW_PROC_ID=11 PROC_CHIP_ID=1 EC=0x21 OK
-CORE[9]: PIR=-268435456 RES=-268435456 OK (8 threads)
+CORE[9]: PIR=000000f0 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[10]: HW_PROC_ID=13 PROC_CHIP_ID=2 EC=0x21 OK
-CORE[10]: PIR=671612928 RES=671612928 OK (8 threads)
+CORE[10]: PIR=00000828 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[11]: HW_PROC_ID=14 PROC_CHIP_ID=2 EC=0x21 OK
-CORE[11]: PIR=805830656 RES=805830656 OK (8 threads)
+CORE[11]: PIR=00000830 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[12]: HW_PROC_ID=15 PROC_CHIP_ID=2 EC=0x21 OK
-CORE[12]: PIR=1611137024 RES=1611137024 OK (8 threads)
+CORE[12]: PIR=00000860 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[13]: HW_PROC_ID=16 PROC_CHIP_ID=2 EC=0x21 OK
-CORE[13]: PIR=1745354752 RES=1745354752 OK (8 threads)
+CORE[13]: PIR=00000868 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[14]: HW_PROC_ID=17 PROC_CHIP_ID=2 EC=0x21 OK
-CORE[14]: PIR=1879572480 RES=1879572480 OK (8 threads)
+CORE[14]: PIR=00000870 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[15]: HW_PROC_ID=18 PROC_CHIP_ID=3 EC=0x21 OK
-CORE[15]: PIR=-1610088448 RES=-1610088448 OK (8 threads)
+CORE[15]: PIR=000008a0 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[16]: HW_PROC_ID=19 PROC_CHIP_ID=3 EC=0x21 OK
-CORE[16]: PIR=-1475870720 RES=-1475870720 OK (8 threads)
+CORE[16]: PIR=000008a8 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[17]: HW_PROC_ID=20 PROC_CHIP_ID=3 EC=0x21 OK
-CORE[17]: PIR=-1341652992 RES=-1341652992 OK (8 threads)
+CORE[17]: PIR=000008b0 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[18]: HW_PROC_ID=22 PROC_CHIP_ID=3 EC=0x21 OK
-CORE[18]: PIR=-402128896 RES=-402128896 OK (8 threads)
+CORE[18]: PIR=000008e8 OK (8 threads)
Cache: I=32 D=64/512/8192/0
CORE[19]: HW_PROC_ID=23 PROC_CHIP_ID=3 EC=0x21 OK
-CORE[19]: PIR=-267911168 RES=-267911168 OK (8 threads)
+CORE[19]: PIR=000008f0 OK (8 threads)
Cache: I=32 D=64/512/8192/0
IPLPARAMS: 1 serial ports in array
IPLPARAMS: Serial 0 rsrc: 2a00 loc: U78CB.001.WZS00AL-P1-C1-T1
--
2.7.4
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