[Skiboot] [PATCH 1/1] vas: Set mmio enable bits in DD2
Michael Neuling
michael.neuling at au1.ibm.com
Sat Aug 19 10:10:17 AEST 2017
On Thu, 2017-08-17 at 22:35 -0700, Sukadev Bhattiprolu wrote:
> From b32b629700013c1651789d93bc8e5e4d4967c75c Mon Sep 17 00:00:00 2001
> From: Sukadev Bhattiprolu <sukadev at linux.vnet.ibm.com>
> Date: Thu, 17 Aug 2017 17:50:24 -0700
> Subject: [PATCH 1/1] vas: Set mmio enable bits in DD2
This is not the right way to format patches on the list. Drop all this above.
> POWER9 DD2 added some new "enable" bits that must be set for VAS to
> work. These bits were unused in DD1.
>
> Signed-off-by: Sukadev Bhattiprolu <sukadev at linux.vnet.ibm.com>
Acked-By: Michael Neuling <mikey at neuling.org>
> ---
> core/vas.c | 3 +++
> include/vas.h | 3 +++
> 2 files changed, 6 insertions(+), 0 deletions(-)
>
> diff --git a/core/vas.c b/core/vas.c
> index a00dc26..bba9509 100644
> --- a/core/vas.c
> +++ b/core/vas.c
> @@ -103,6 +103,9 @@ static int init_north_ctl(struct proc_chip *chip)
>
> val = SETFIELD(VAS_64K_MODE_MASK, val, true);
> val = SETFIELD(VAS_ACCEPT_PASTE_MASK, val, true);
> + val = SETFIELD(VAS_ENABLE_WC_MMIO_BAR, val, true);
> + val = SETFIELD(VAS_ENABLE_UWC_MMIO_BAR, val, true);
> + val = SETFIELD(VAS_ENABLE_RMA_MMIO_BAR, val, true);
>
> return vas_scom_write(chip, VAS_MISC_N_CTL, val);
> }
> diff --git a/include/vas.h b/include/vas.h
> index da19645..bc0aff7 100644
> --- a/include/vas.h
> +++ b/include/vas.h
> @@ -131,6 +131,9 @@ extern __attrconst uint64_t vas_get_wcbs_bar(int chipid);
> #define VAS_64K_MODE_MASK PPC_BIT(0)
> #define VAS_ACCEPT_PASTE_MASK PPC_BIT(1)
> #define VAS_QUIESCE_REQ_MASK PPC_BIT(4)
> +#define VAS_ENABLE_WC_MMIO_BAR PPC_BIT(6)
> +#define VAS_ENABLE_UWC_MMIO_BAR PPC_BIT(7)
> +#define VAS_ENABLE_RMA_MMIO_BAR PPC_BIT(8)
> #define VAS_HMI_ACTIVE_MASK PPC_BIT(58)
> #define VAS_RG_IDLE_MASK PPC_BIT(59)
>
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