[Skiboot] [PATCH v3 02/10] npu2: Fix indirect SCOM addresses

[Reza Arbab]

Change these values for POWER9 DD2, but keep backwards compatibility.

Signed-off-by: Reza Arbab <arbab at linux.vnet.ibm.com>
Acked-by: Alistair Popple <alistair at popple.id.au>
Reviewed-by: Andrew Donnellan <andrew.donnellan at au1.ibm.com>
Cc: Frederic Barrat <fbarrat at linux.vnet.ibm.com>
---
 hw/npu2.c           | 14 +++++++++++---
 include/npu2-regs.h |  6 ++++--
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/hw/npu2.c b/hw/npu2.c
index a986652..daee6e3 100644
--- a/hw/npu2.c
+++ b/hw/npu2.c
@@ -75,26 +75,34 @@ static bool is_p9dd1(void)
 static void npu2_scom_set_addr(uint64_t gcid, uint64_t scom_base,
 			       uint64_t addr, uint64_t size)
 {
+	uint64_t isa = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_ADDR :
+				    NPU2_MISC_SCOM_IND_SCOM_ADDR;
+
 	addr = SETFIELD(NPU2_MISC_DA_ADDR, 0ull, addr);
 	addr = SETFIELD(NPU2_MISC_DA_LEN, addr, size);
-	xscom_write(gcid, scom_base + NPU2_MISC_SCOM_IND_SCOM_ADDR, addr);
+	xscom_write(gcid, scom_base + isa, addr);
 }
 
 static void npu2_scom_write(uint64_t gcid, uint64_t scom_base,
 			    uint64_t reg, uint64_t size,
 			    uint64_t val)
 {
+	uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA :
+				    NPU2_MISC_SCOM_IND_SCOM_DATA;
+
 	npu2_scom_set_addr(gcid, scom_base, reg, size);
-	xscom_write(gcid, scom_base + NPU2_MISC_SCOM_IND_SCOM_DATA, val);
+	xscom_write(gcid, scom_base + isd, val);
 }
 
 static uint64_t npu2_scom_read(uint64_t gcid, uint64_t scom_base,
 			       uint64_t reg, uint64_t size)
 {
 	uint64_t val;
+	uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA :
+				    NPU2_MISC_SCOM_IND_SCOM_DATA;
 
 	npu2_scom_set_addr(gcid, scom_base, reg, size);
-	xscom_read(gcid, scom_base + NPU2_MISC_SCOM_IND_SCOM_DATA, &val);
+	xscom_read(gcid, scom_base + isd, &val);
 
 	return val;
 }
diff --git a/include/npu2-regs.h b/include/npu2-regs.h
index 2ddfd4b..4b86f6f 100644
--- a/include/npu2-regs.h
+++ b/include/npu2-regs.h
@@ -441,11 +441,13 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask);
 #define NPU2_XTS_MMIO_ATSD_STATUS		0x010
 
 /* ALTD SCOM addresses */
-#define NPU2_MISC_SCOM_IND_SCOM_ADDR		0x38e
+#define NPU2_DD1_MISC_SCOM_IND_SCOM_ADDR	0x38e
+#define NPU2_MISC_SCOM_IND_SCOM_ADDR		0x68e
 #define  NPU2_MISC_DA_ADDR			PPC_BITMASK(0, 23)
 #define  NPU2_MISC_DA_LEN			PPC_BITMASK(24, 25)
 #define   NPU2_MISC_DA_LEN_4B			2
 #define   NPU2_MISC_DA_LEN_8B			3
-#define NPU2_MISC_SCOM_IND_SCOM_DATA   		0x38f
+#define NPU2_DD1_MISC_SCOM_IND_SCOM_DATA	0x38f
+#define NPU2_MISC_SCOM_IND_SCOM_DATA		0x68f
 
 #endif /* __NPU2_REGS_H */
-- 
1.8.3.1