[Skiboot] [PATCH v3 00/10] npu2: Updates for POWER9 DD2

Reza Arbab arbab at linux.vnet.ibm.com
Tue Aug 1 12:36:56 AEST 2017

The POWER9 NPU design has been updated in DD2. This set adapts to the changes,
retaining compatibility with DD1.

Lightly test driven on some of the new hardware. The GPU driver can load again
and seems happy.

* Refactor patch "npu2: Use read-modify-write in npu2_assign_gmb()".

* https://lists.ozlabs.org/pipermail/skiboot/2017-July/008364.html
* Integrate feedback from Alistair and Andrew.

* https://lists.ozlabs.org/pipermail/skiboot/2017-July/008207.html
Reza Arbab (10):
  npu2: Add a function to detect POWER9 DD1
  npu2: Fix indirect SCOM addresses
  npu2: Fix NPU/PHY0/PHY1 stack order
  npu2: Rename variable in npu2_assign_gmb()
  npu2: Use read-modify-write in npu2_assign_gmb()
  npu2: Add NPU2_GPU1_MEM_BAR
  npu2: Adjust content of the GENID BAR
  npu2: Adjust content of the NTL BAR
  npu2: Set the XTS config2 register
  npu2: Allow POWER9 DD2 in ec level check

 hw/npu2.c           | 118 ++++++++++++++++++++++++++++++++++------------------
 include/npu2-regs.h |  19 ++++++---
 2 files changed, 91 insertions(+), 46 deletions(-)


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