[Skiboot] [PATCH V2 0/5] capi: Add support for Coherent Accelerator Interface Architecture 2.0

[Frederic Barrat]

< from Christophe> note that a v3 of this patch is (almost!) ready. 
There's still that one pesky little pb... So no need to consider this 
version for merging.



Le 31/03/2017 à 18:52, Christophe Lombard a écrit :
> This series implements phb4 backend to support card which supports the
> Coherent Accelerator Interface Architecture 2.0.
>
> It requires IBM Power9 system and the Power Service Layer, version 9.
> The PSL provides the address translation and system memory cache for
> CAIA compliant Accelerators.
> the PSL attaches to the IBM Processor chip through the PCIe link using
> the PSL-specific “CAPI Protocol” Transaction Layer Packets.
> The PSL and CAPP communicate using PowerBus packets.
> When using a PCIe link the PCIe Host Bridge (PHB) decodes the CAPI
> Protocol Packets from the PSL and forwards them as PowerBus data
> packets. The PSL also has an optional DMA feature which allows the AFU
> to send native PCIe reads and writes to the Processor.
>
> The code for PHB4 (Caia2) is based on PHB3 (Caia2) for the commun
> functionalities as the synchronization of the timebase and the
> preload/load of the CAPP microcode.
>
> CAPP Connections for PHB4
> • CAPP0 is located in unit EN and is connected to pci-e unit 0 (PHB0).
> • CAPP1 is located in unit ES and is connected to pci-e unit 2 (PHB3).
>
> The first patch externalizes the chiptod code. It will be used for PHB3
> and PHB4.
> The patch 2 moves in a specific file the definitions of the CAPP
> registers for PHB3.
> The patch 3 initializes the CAPP registers and enables the CAPP Mode of
> the PEC.
> The patch 4 loads the CAPP microcode for PHB4,
> and the patch 5 handles HMI events.
>
> Tested on Simulation environment.
>
> Changelog[v2]
>  - Rebase to latest upstream.
>  - Integrate comments from Andrew Donnellan and Frederic Barrat.
>  - patch3: - Add new functions to cover recovery and disable mode.
> 	   - Update the initialization of CAPP registers.
>  - patch4: - Rewrote the function capp_load_ucode().
> 	   - Move capi_lock definition to a right place.
> 	   - Move away from printf to an appropriate prlog macro.
> 	   - Add CAPP resource ID: CAPP_IDX_NIMBUS_DD10
> 	   - Trigger a creset to disable CAPI mode on kernel shutdown.
>
> Christophe Lombard (5):
>   capi: Externalize capp timebase synchronization
>   capi: Move phb3 capp registers to specialized files
>   capi: Enable capi mode
>   capi: Load capp microcode
>   capi: Handle HMI events
>
>  core/hmi.c          | 117 ++++--------
>  core/init.c         |   2 +-
>  hw/Makefile.inc     |   2 +-
>  hw/capp.c           | 238 +++++++++++++++++++++++++
>  hw/chiptod.c        |  40 ++---
>  hw/fsp/fsp.c        |   2 +
>  hw/phb3.c           | 239 +++++--------------------
>  hw/phb4.c           | 504 +++++++++++++++++++++++++++++++++++++++++++++++++++-
>  include/capp.h      |  62 ++++---
>  include/chip.h      |   1 +
>  include/chiptod.h   |   4 +-
>  include/phb3-capp.h |  52 ++++++
>  include/phb4-capp.h |  63 +++++++
>  include/phb4-regs.h |   8 +-
>  include/phb4.h      |   1 +
>  include/skiboot.h   |   3 +-
>  16 files changed, 997 insertions(+), 341 deletions(-)
>  create mode 100644 hw/capp.c
>  create mode 100644 include/phb3-capp.h
>  create mode 100644 include/phb4-capp.h
>