[Skiboot] [PATCH v8 04/10] skiboot: Nest IMC macro definitions

[Madhavan Srinivasan]

From: Hemant Kumar <hemant at linux.vnet.ibm.com>

Add the macros needed for Nest IMC (In Memory Collection)
instrumentation support by creating a new file in include/ called
"imc.h". Also, add a header "nest_imc.h" containing an array of
possible list of nest PMUs. These macros are needed to discover the
catalog subpartition, enable and disable the nest IMC instrumentation.

Signed-off-by: Hemant Kumar <hemant at linux.vnet.ibm.com>
Reviewed-by: Oliver O'Halloran <oohall at gmail.com>
[maddy: Removed nest_imc.h and updated few macros]
Signed-off-by: Madhavan Srinivasan <maddy at linux.vnet.ibm.com>

Signed-off-by: Madhavan Srinivasan <maddy at linux.vnet.ibm.com>
---
 include/imc.h | 118 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 118 insertions(+)
 create mode 100644 include/imc.h

diff --git a/include/imc.h b/include/imc.h
new file mode 100644
index 000000000000..3e3205431981
--- /dev/null
+++ b/include/imc.h
@@ -0,0 +1,118 @@
+/* Copyright 2016 IBM Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *	http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ * implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * IMC (In-Memory Collection) :
+ * Power9 has IMC instrumentation support with which several metrics of the
+ * platform can be monitored. These metrics are backed by the
+ * Performance Monitoring Units (PMUs) and their counters.
+ * IMC counters run continuously from startup to shutdown and hence, the
+ * name and data from these counters are fed directly into a pre-defined
+ * memory location.
+ *
+ * Depending on the counters' location and monitoring engines, they are
+ * classified into three domains :
+ * Nest IMC, core IMC and thread IMC.
+ *
+ * Nest Counters :
+ * Nest counters are per-chip counters and can help in providing utilisation
+ * metrics like memory bandwidth, Xlink/Alink bandwidth etc.
+ * A microcode in OCC programs the nest counters and moves counter values to
+ * per chip HOMER region in a fixed offset for each unit. Engine has a
+ * control block structure for communication with Hypervisor(Host OS).
+ */
+
+#ifndef __IMC_H
+#define __IMC_H
+
+/*
+ * Control Block structure offset in HOMER nest Region
+ */
+#define P9_CB_STRUCT_OFFSET		0x1BFC00
+#define P9_CB_STRUCT_CMD		0x1BFC08
+#define P9_CB_STRUCT_SPEED		0x1BFC10
+
+/* Nest microcode Status */
+#define NEST_IMC_PAUSE		0x2
+#define NEST_IMC_RESUME		0x1
+#define NEST_IMC_NOP		0
+
+/*
+ * Control Block Structure:
+ *
+ * Name          Producer        Consumer        Values  Desc
+ * IMCRunStatus   IMC Code       Hypervisor      0       Initializing
+ *                               (Host OS)       1       Running
+ *                                               2       Paused
+ *
+ * IMCCommand     Hypervisor     IMC Code        0       NOP
+ *                                               1       Resume
+ *                                               2       Pause
+ *                                               3       Clear and Restart
+ *
+ * IMCCollection Hypervisor      IMC Code        0       128us
+ * Speed					 1       256us
+ *                                               2       1ms
+ *                                               3       4ms
+ *                                               4       16ms
+ *                                               5       64ms
+ *                                               6       256ms
+ *                                               7       1000ms
+ *
+ * IMCAvailability IMC Code      Hypervisor      -       64-bit value describes
+ *                                                       the Vector Nest PMU
+ *                                                       availability.
+ *                                                       Bits 0-47 denote the
+ *                                                       availability of 48 different
+ *                                                       nest units.
+ *                                                       Rest are reserved. For details
+ *                                                       regarding which bit belongs
+ *                                                       to which unit, see
+ *                                                       include/nest_imc.h.
+ *                                                       If a bit is unset (0),
+ *                                                       then, the corresponding unit
+ *                                                       is unavailable. If its set (1),
+ *                                                       then, the unit is available.
+ *
+ * IMCRun Mode    Hypervisor     IMC Code        0       Normal Mode (Monitor Mode)
+ *                                               1       Debug Mode 1 (PB)
+ *                                               2       Debug Mode 2 (MEM)
+ *                                               3       Debug Mode 3 (PCIE)
+ *                                               4       Debug Mode 4 (CAPP)
+ *                                               5       Debug Mode 5 (NPU 1)
+ *                                               6       Debug Mode 6 (NPU 2)
+ */
+struct imc_chip_cb
+{
+	u64 imc_chip_run_status;
+	u64 imc_chip_command;
+	u64 imc_chip_collection_speed;
+	u64 imc_chip_avl_vector;
+	u64 imc_chip_run_mode;
+};
+
+/* Size of IMC dtb LID (256KBytes) */
+#define IMC_DTB_SIZE		0x40000
+
+/*
+ * Nest IMC operations
+ */
+#define NEST_IMC_ENABLE			0x1
+#define NEST_IMC_DISABLE		0x2
+
+#define MAX_AVL		48
+
+#endif /* __IMC_H */
-- 
2.7.4