[Skiboot] [PATCH 1/2] hw/npu: program NPU BUID reg properly

[Stewart Smith]

Alistair Popple <alistair at popple.id.au> writes:
> From: Milton Miller <miltonm at us.ibm.com>
>
> The NPU BUID register was incorrectly programmed resulting in npu
> interrupt level 0 causing a PB_CENT_CRESP_ADDR_ERROR checkstop,
> and irqs from npus in odd chips being aliased to and processed
> as the interrupts from the corresponding npu on the even chips.
>
> The documentation for the BUID register is confusing, describing
> required values of some bits and bits of differing meaning within
> contained within one field.
>
> This patch seperates the per-irq-level irq enable mask from the
> documented buid base field, leaving the buid base as the part that
> is directly compared.  It documents the buid as the boundary of a
> block of 16 sources (in the form of a 4 bit shift), and documents
> that some bits are sourced from another register and are always
> compared to that register, so they are not required to be set in
> the base and mask fields.
>
> Fixes: cc61799 Nvlink: Add NPU PHB functions
> Signed-off-by: Milton Miller <miltonm at us.ibm.com>
> Signed-off-by: Alistair Popple <alistair at popple.id.au>

Thanks!

Both patches merged

merged to master as of ac83440c8241902d2c32410050a2fd1e96b20fcf
merged to 5.3.x as of fc7484515a357a08d44a250f0b701b6edb093653

i guess it's time to do a 5.3.3 now :)

-- 
Stewart Smith
OPAL Architect, IBM.