[Skiboot] [PATCH 2/2] hw/npu: assert the NPU irq min is aligned.

[Alistair Popple]

From: Milton Miller <miltonm at us.ibm.com>

The hardware enforces the buid range is on a 16 irsn boundary
even though there are only 8 irqs.  Enforce that here and show
where the value comes from when programming the lsi source id
field in the npu register block.

Signed-off-by: Milton Miller <miltonm at us.ibm.com>
Signed-off-by: Alistair Popple <alistair at popple.id.au>
---
 hw/npu.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/npu.c b/hw/npu.c
index 11e8b97..a9a167e 100644
--- a/hw/npu.c
+++ b/hw/npu.c
@@ -26,6 +26,7 @@
 #include <device.h>
 #include <ccan/str/str.h>
 #include <ccan/array_size/array_size.h>
+#include <ccan/build_assert/build_assert.h>
 #include <affinity.h>
 #include <npu-regs.h>
 #include <npu.h>
@@ -800,7 +801,8 @@ static void npu_hw_init(struct npu *p)
 {
 	/* 3 MMIO setup for AT */
 	out_be64(p->at_regs + NPU_LSI_SOURCE_ID,
-		 SETFIELD(NPU_LSI_SRC_ID_BASE, 0ul, 0x7f));
+		 SETFIELD(NPU_LSI_SRC_ID_BASE, 0ul, NPU_LSI_IRQ_MIN >> 4));
+	BUILD_ASSERT((NPU_LSI_IRQ_MIN & 0x07F0) == NPU_LSI_IRQ_MIN);
 	out_be64(p->at_regs + NPU_INTREP_TIMER, 0x0ul);
 	npu_ioda_reset(&p->phb, false);
 }
-- 
2.1.4