[Skiboot] [PATCH v2 1/6] VAS: Define macros needed by VAS
Oliver O'Halloran
oohall at gmail.com
Wed Nov 23 16:38:12 AEDT 2016
On Wed, Nov 23, 2016 at 1:00 PM, Sukadev Bhattiprolu
<sukadev at linux.vnet.ibm.com> wrote:
> Define macros for the various Base Address Regions and Register fields
> that are needed by VAS.
>
> Signed-off-by: Sukadev Bhattiprolu <sukadev at linux.vnet.ibm.com>
> ---
> core/Makefile.inc | 2 +-
> core/init.c | 4 ++
> core/vas.c | 20 +++++++
> include/vas.h | 156 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 181 insertions(+), 1 deletion(-)
> create mode 100644 core/vas.c
> create mode 100644 include/vas.h
>
> diff --git a/core/Makefile.inc b/core/Makefile.inc
> index 9223af1..f41617d 100644
> --- a/core/Makefile.inc
> +++ b/core/Makefile.inc
> @@ -8,7 +8,7 @@ CORE_OBJS += pci-opal.o fast-reboot.o device.o exceptions.o trace.o affinity.o
> CORE_OBJS += vpd.o hostservices.o platform.o nvram.o nvram-format.o hmi.o
> CORE_OBJS += console-log.o ipmi.o time-utils.o pel.o pool.o errorlog.o
> CORE_OBJS += timer.o i2c.o rtc.o flash.o sensor.o ipmi-opal.o
> -CORE_OBJS += flash-subpartition.o
> +CORE_OBJS += flash-subpartition.o vas.o
>
> ifeq ($(SKIBOOT_GCOV),1)
> CORE_OBJS += gcov-profiling.o
> diff --git a/core/init.c b/core/init.c
> index 9d4ab60..2af5427 100644
> --- a/core/init.c
> +++ b/core/init.c
> @@ -45,6 +45,7 @@
> #include <sensor.h>
> #include <xive.h>
> #include <nvram.h>
> +#include <vas.h>
> #include <libstb/stb.h>
> #include <libstb/container.h>
>
> @@ -909,6 +910,9 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt)
> phb3_preload_capp_ucode();
> start_preload_kernel();
>
> + /* Virtual Accelerator Switchboard */
> + init_vas();
> +
> /* NX init */
> nx_init();
>
> diff --git a/core/vas.c b/core/vas.c
> new file mode 100644
> index 0000000..eefb40d
> --- /dev/null
> +++ b/core/vas.c
> @@ -0,0 +1,20 @@
> +/* Copyright 2013-2016 IBM Corp.
> + *
> + * Licensed under the Apache License, Version 2.0 (the "License");
> + * you may not use this file except in compliance with the License.
> + * You may obtain a copy of the License at
> + *
> + * http://www.apache.org/licenses/LICENSE-2.0
> + *
> + * Unless required by applicable law or agreed to in writing, software
> + * distributed under the License is distributed on an "AS IS" BASIS,
> + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
> + * implied.
> + * See the License for the specific language governing permissions and
> + * limitations under the License.
> + */
> +#include <vas.h>
> +
> +__attrconst void init_vas(void)
> +{
> +}
Can you fold the Makefile changes and the vas.c stuff into the next
patch in this series? It's just noise here and the next patch in the
series replaces vas.c entirely.
> diff --git a/include/vas.h b/include/vas.h
> new file mode 100644
> index 0000000..ab1064a
> --- /dev/null
> +++ b/include/vas.h
> @@ -0,0 +1,156 @@
> +/* Copyright 2013-2016 IBM Corp.
> + *
> + * Licensed under the Apache License, Version 2.0 (the "License");
> + * you may not use this file except in compliance with the License.
> + * You may obtain a copy of the License at
> + *
> + * http://www.apache.org/licenses/LICENSE-2.0
> + *
> + * Unless required by applicable law or agreed to in writing, software
> + * distributed under the License is distributed on an "AS IS" BASIS,
> + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
> + * implied.
> + * See the License for the specific language governing permissions and
> + * limitations under the License.
> + */
> +
> +#ifndef __VAS_H
> +#define __VAS_H
> +
> +#include <xscom.h>
> +
> +/*
> + * Abbreviations used in VAS:
> + * WC: Window Context
> + * WCM: Window Context MMIO
> + * UWC: OS/User Window Context
> + * UWCM: OS/User Window Context MMIO
> + * WIDM: Window ID MMIO
> + * BAR: Base Address Register
> + * BAMR: Base Address Mask Register
> + * N (S): North (South)
> + * CONTS Contents
> + * FIR: Fault Isolation Register
> + */
> +
> +extern void init_vas(void);
> +
> +/*
> + * HVWC and UWC BAR.
> + *
> + * A Power node can have (upto?) 8 Power chips.
> + *
> + * There is one instance of VAS in each Power chip. Each instance of VAS
> + * has 64K windows, which can be used to send/receive messages from
> + * software threads and coprocessors.
> + *
> + * Each window is described by two types of window contexts:
> + *
> + * Hypervisor Window Context (HVWC) of size VAS_HVWC_SIZE bytes
> + * OS/User Window Context (UWC) of size VAS_UWC_SIZE bytes.
> + *
> + * A window context can be viewed as a set of 64-bit registers. The settings
> + * of these registers control/determine the behavior of the VAS hardware
> + * when messages are sent/received through the window.
> + *
> + * Each Power chip i.e each instance of VAS, is assigned two distinct ranges
> + * (one for each type of context) of Power-bus addresses (aka Base Address
> + * Region or BAR) which can be used to access the window contexts in that
> + * instance of VAS.
> + *
> + * From the Power9 MMIO Ranges Spreadsheet:
> + *
> + * The HVWC BAR is of size 0x40000000000. For chip 0, the HVWC BAR begins
> + * at 0x6019000000000ULL, for chip 1 at 0x0006059000000000 etc.
> + *
> + * i.e the HVWC for each of the 64K windows on chip 0 can be accessed at the
> + * address 0x6019000000000ULL, and HVWC for the 64K windows on chip 1 can be
> + * accessed at the address 0x0006059000000000 and so on.
> + *
> + * Similarly, the UWC BAR is also of size 0x40000000000. For chip 0, UWC BAR
> + * begins at 0x0006019100000000, for chip 1 at 0x0006059100000000 etc.
> + *
> + * Following macros specify the HVWC and UWC BARs for chip 0. The BARs for
> + * the other chips are computed in get_hvwc_mmio_bar() and get_uwc_mmio_bar().
> + */
> +#define VAS_HVWC_MMIO_BAR_BASE 0x0006019100000000ULL
> +#define VAS_HVWC_MMIO_BAR_SIZE 0x40000000000
> +
> +#define VAS_UWC_MMIO_BAR_BASE 0x0006019000000000ULL
> +#define VAS_UWC_MMIO_BAR_SIZE 0x40000000000
> +
> +/* Window Context Backing Store Size */
> +#define VAS_WCBS_SIZE 0x800000 /* 8MB */
> +
> +/* Window context size of each window */
> +#define VAS_WC_SIZE 512
> +
> +/*
> + * SCOM Base Address from P9 SCOM Assignment spreadsheet
> + */
> +#define VAS_SCOM_BASE_ADDR 0x03011800
> +
> +/*
> + * NOTE: VAS_SCOM_BASE_ADDR (0x3011840) includes the SCOM ring of 6. So,
> + * setting the ring to 0 here.
> + *
> + * The satellite and offset values below are from "Table 3.1 VAS
> + * Internal Register Listing" of the P9 VAS Workbook.
> + */
> +#define VAS_P9_SAT(sat, offset) XSCOM_SAT(0x0, sat, offset)
> +
> +#define VAS_FIR0 VAS_P9_SAT(0x0, 0x0)
> +#define VAS_FIR1 VAS_P9_SAT(0x0, 0x1)
> +#define VAS_FIR2 VAS_P9_SAT(0x0, 0x2)
> +#define VAS_FIR3 VAS_P9_SAT(0x0, 0x3)
> +#define VAS_FIR4 VAS_P9_SAT(0x0, 0x4)
> +#define VAS_FIR5 VAS_P9_SAT(0x0, 0x5)
> +#define VAS_FIR6 VAS_P9_SAT(0x0, 0x6)
> +#define VAS_FIR7 VAS_P9_SAT(0x0, 0x7)
> +
> +#define VAS_WCM_BAR VAS_P9_SAT(0x0, 0xA)
> +#define VAS_UWCM_BAR VAS_P9_SAT(0x0, 0xB)
> +#define VAS_BUF_CTL VAS_P9_SAT(0x0, 0xC)
> +#define VAS_MISC_N_CTL VAS_P9_SAT(0x0, 0xD)
> +#define VAS_RMA_BAR VAS_P9_SAT(0x0, 0xE)
> +#define VAS_RMA_BAMR VAS_P9_SAT(0x0, 0xF)
> +#define VAS_WIDM_CTL VAS_P9_SAT(0x0, 0x29)
> +#define VAS_WIDM_DATA VAS_P9_SAT(0x0, 0x2A)
> +#define VAS_IN_CERR_RPT_CONTS VAS_P9_SAT(0x0, 0x2B)
> +#define VAS_RG_CERR_RPT_CONTS VAS_P9_SAT(0x0, 0x2B)
> +#define VAS_WIDM_ECC VAS_P9_SAT(0x0, 0x31)
> +
> +#define VAS_WCBS_BAR VAS_P9_SAT(0x1, 0x0)
> +#define VAS_CQ_CERR_RPT_CONTS VAS_P9_SAT(0x1, 0x8)
> +#define VAS_WC_CERR_RPT_CONTS VAS_P9_SAT(0x1, 0x9)
> +#define VAS_EG_CERR_RPT_CONTS VAS_P9_SAT(0x1, 0xA)
> +
> +#define VAS_PB_CFG0 VAS_P9_SAT(0x1, 0xD)
> +#define VAS_PB_CFG1 VAS_P9_SAT(0x1, 0xE)
> +#define VAS_MISC_S_CTL VAS_P9_SAT(0x1, 0xF)
> +
> +#define VAS_BUF_CTL_FREE_COUNT PPC_BITMASK(49:55)
> +#define VAS_BUF_CTL_USED_COUNT PPC_BITMASK(57:63)
> +#define VAS_RMA_BAR_ADDR PPC_BITMASK(8, 51)
> +#define VAS_RMA_BAMR_MASK PPC_BITMASK(8, 51)
> +
> +/* Some VAS Miscellaneous Status and North Control Register bits. */
> +#define VAS_64K_MODE_MASK PPC_BIT(0)
> +#define VAS_64K_MODE 1
> +#define VAS_ACCEPT_PASTE_MASK PPC_BIT(1)
> +#define VAS_ACCEPT_PASTE 1
> +#define VAS_QUIESCE_REQ_MASK PPC_BIT(4)
> +#define VAS_QUIESCE_REQ 1
> +#define VAS_HMI_ACTIVE_MASK PPC_BIT(58)
> +#define VAS_HMI_ACTIVE 1
> +#define VAS_RG_IDLE_MASK PPC_BIT(59)
> +#define VAS_RG_IDLE 1
What's going on here? I understand defining the _MASK macros, but why
define all the others to 1?
> +
> +/* Some PowerBus Configuration Register 0 Bits */
> +#define VAS_CQSCOM_HANG_POLL_MAX PPC_BITMASK(7, 10)
> +#define VAS_CQSCOM_HANG_NX_MAX PPC_BITMASK(15, 18)
> +
> +#define VAS_RMA_BAR_ADDR_MASK PPC_BITMASK(8, 51)
> +#define VAS_RMA_BAMR_ADDR_MASK PPC_BITMASK(8, 51)
> +
> +#endif
> --
> 2.7.4
>
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