[Skiboot] [RFC PATCH 7/7] VAS: Define OPAL_VAS_GET_TRIGGER_PORT interface

[Sukadev Bhattiprolu]

Implement the OPAL_VAS_GET_TRIGGER_PORT interface to retrieve the
trigger port assigned to a window. Linux kernel uses this port to
register an interrupt handler for copy/paste requests submitted to
this window.

Signed-off-by: Sukadev Bhattiprolu <sukadev at linux.vnet.ibm.com>
---
 core/vas.c         |   53 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 include/chip.h     |    1 +
 include/opal-api.h |    3 +-
 3 files changed, 56 insertions(+), 1 deletions(-)

diff --git a/core/vas.c b/core/vas.c
index e7079bb..cc943e1 100644
--- a/core/vas.c
+++ b/core/vas.c
@@ -16,6 +16,7 @@
 #include <skiboot.h>
 #include <chip.h>
 #include <xscom.h>
+#include <xive.h>
 #include <vas.h>
 
 #undef VAS_VERBOSE_DEBUG
@@ -118,6 +119,33 @@ static int opal_vas_read_fir(uint32_t chip_id, int idx, uint64_t *val)
 }
 opal_call(OPAL_VAS_READ_FIR, opal_vas_read_fir, 3);
 
+static int opal_vas_get_trigger_port(uint32_t chip_id, int idx, uint32_t *irq,
+			uint64_t *port)
+{
+	struct proc_chip *chip;
+
+	chip = get_chip(chip_id);
+	if (!chip)
+		return OPAL_PARAMETER;
+
+	if (!chip->vas_irq_base) {
+		vas_vdbg("ERROR: chip %d vas_irq_base NULL!\n", chip->id);
+		return OPAL_PARAMETER;
+	}
+
+	if (idx >= max_win_per_chip) {
+		vas_vdbg("ERROR: idx %d, max_win_per_chip %d\n", idx,
+				max_win_per_chip);
+		return OPAL_PARAMETER;
+	}
+
+	*irq = chip->vas_irq_base + idx;
+	*port = (uint64_t)xive_get_trigger_port(*irq);
+
+	return OPAL_SUCCESS;
+}
+opal_call(OPAL_VAS_GET_TRIGGER_PORT, opal_vas_get_trigger_port, 4);
+
 static int init_north_ctl(struct proc_chip *chip)
 {
 	uint64_t val = 0ULL;
@@ -283,6 +311,28 @@ static int init_windows(struct proc_chip *chip)
 	return 0;
 }
 
+/* TODO: Do we need to free these at some point ??? */
+static int alloc_irqs(struct proc_chip *chip)
+{
+	int i;
+	int align = 128;
+	uint32_t irqbase;
+
+	irqbase = xive_alloc_ipi_irqs(chip->id, max_win_per_chip, align);
+
+	if (irqbase == XIVE_IRQ_ERROR)
+		return -1;
+
+	for (i = 0; i < max_win_per_chip; i++) {
+		vas_vdbg("trigger port[%d]: 0x%p\n", i,
+				xive_get_trigger_port(irqbase+i));
+	}
+
+	chip->vas_irq_base = irqbase;
+
+	return 0;
+}
+
 static int init_one_chip(struct proc_chip *chip)
 {
 	if (init_wcbs(chip) || init_wcm(chip) || init_uwcm(chip))
@@ -296,6 +346,9 @@ static int init_one_chip(struct proc_chip *chip)
 	if (init_rma(chip) || init_windows(chip))
 		goto out;
 
+	if (alloc_irqs(chip))
+		goto out;
+
 	printf("VAS: Initialized chip %d\n", chip->id);
 	return 0;
 
diff --git a/include/chip.h b/include/chip.h
index 61b413c..aaebce4 100644
--- a/include/chip.h
+++ b/include/chip.h
@@ -205,6 +205,7 @@ struct proc_chip {
 
 	/* Used by hw/xive.c */
 	struct xive		*xive;
+	uint32_t		vas_irq_base;
 };
 
 extern uint32_t pir_to_chip_id(uint32_t pir);
diff --git a/include/opal-api.h b/include/opal-api.h
index 9705ebd..6f930cb 100644
--- a/include/opal-api.h
+++ b/include/opal-api.h
@@ -182,7 +182,8 @@
 #define OPAL_PCI_TCE_KILL			126
 #define OPAL_NMMU_SET_PTCR			127
 #define OPAL_VAS_READ_FIR			128
-#define OPAL_LAST				128
+#define OPAL_VAS_GET_TRIGGER_PORT		129
+#define OPAL_LAST				129
 
 /* Device tree flags */
 
-- 
1.7.1