[Skiboot] [PATCH V2 4/6] chiptod: Sync timebase in both CAPP units on Naples

[Philippe Bergheaud]

Naples has two capp units. Use the xscom register address offset
to operate on the right capp unit.

Signed-off-by: Philippe Bergheaud <felix at linux.vnet.ibm.com>
---
V2:
  - Add reg_offset to CAPP_TB in chiptod_capp_timebase_sync

 hw/chiptod.c      | 34 +++++++++++++++++-----------------
 hw/phb3.c         |  2 +-
 include/chiptod.h |  2 +-
 3 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/hw/chiptod.c b/hw/chiptod.c
index f7427f1..b5f955e 100644
--- a/hw/chiptod.c
+++ b/hw/chiptod.c
@@ -1771,7 +1771,7 @@ void chiptod_init(void)
 
 /* CAPP timebase sync */
 
-static bool chiptod_capp_reset_tb_errors(uint32_t chip_id)
+static bool chiptod_capp_reset_tb_errors(uint32_t chip_id, uint32_t reg_offset)
 {
 	uint64_t tfmr;
 	unsigned long timeout = 0;
@@ -1787,12 +1787,12 @@ static bool chiptod_capp_reset_tb_errors(uint32_t chip_id)
 	tfmr |= SPR_TFMR_TFMR_CORRUPT;
 
 	/* Write CAPP TFMR */
-	xscom_write(chip_id, CAPP_TFMR, tfmr);
+	xscom_write(chip_id, CAPP_TFMR + reg_offset, tfmr);
 
 	/* We have to write "Clear TB Errors" again */
 	tfmr = base_tfmr | SPR_TFMR_CLEAR_TB_ERRORS;
 	/* Write CAPP TFMR */
-	xscom_write(chip_id, CAPP_TFMR, tfmr);
+	xscom_write(chip_id, CAPP_TFMR + reg_offset, tfmr);
 
 	do {
 		if (++timeout >= TIMEOUT_LOOPS) {
@@ -1800,7 +1800,7 @@ static bool chiptod_capp_reset_tb_errors(uint32_t chip_id)
 			return false;
 		}
 		/* Read CAPP TFMR */
-		xscom_read(chip_id, CAPP_TFMR, &tfmr);
+		xscom_read(chip_id, CAPP_TFMR + reg_offset, &tfmr);
 		if (tfmr & SPR_TFMR_TFMR_CORRUPT) {
 			prerror("CAPP: TB error reset: corrupt TFMR!\n");
 			return false;
@@ -1809,20 +1809,20 @@ static bool chiptod_capp_reset_tb_errors(uint32_t chip_id)
 	return true;
 }
 
-static bool chiptod_capp_mod_tb(uint32_t chip_id)
+static bool chiptod_capp_mod_tb(uint32_t chip_id, uint32_t reg_offset)
 {
 	uint64_t timeout = 0;
 	uint64_t tfmr;
 
 	/* Switch CAPP timebase to "Not Set" state */
 	tfmr = base_tfmr | SPR_TFMR_LOAD_TOD_MOD;
-	xscom_write(chip_id, CAPP_TFMR, tfmr);
+	xscom_write(chip_id, CAPP_TFMR + reg_offset, tfmr);
 	do {
 		if (++timeout >= (TIMEOUT_LOOPS*2)) {
 			prerror("CAPP: TB \"Not Set\" timeout\n");
 			return false;
 		}
-		xscom_read(chip_id, CAPP_TFMR, &tfmr);
+		xscom_read(chip_id, CAPP_TFMR + reg_offset, &tfmr);
 		if (tfmr & SPR_TFMR_TFMR_CORRUPT) {
 			prerror("CAPP: TB \"Not Set\" TFMR corrupt\n");
 			return false;
@@ -1857,7 +1857,7 @@ static bool chiptod_wait_for_chip_sync(void)
 	return true;
 }
 
-static bool chiptod_capp_check_tb_running(uint32_t chip_id)
+static bool chiptod_capp_check_tb_running(uint32_t chip_id, uint32_t reg_offset)
 {
 	uint64_t tfmr;
 	uint64_t timeout = 0;
@@ -1868,7 +1868,7 @@ static bool chiptod_capp_check_tb_running(uint32_t chip_id)
 			prerror("CAPP: TB Invalid!\n");
 			return false;
 		}
-		xscom_read(chip_id, CAPP_TFMR, &tfmr);
+		xscom_read(chip_id, CAPP_TFMR + reg_offset, &tfmr);
 		if (tfmr & SPR_TFMR_TFMR_CORRUPT) {
 			prerror("CAPP: TFMR corrupt!\n");
 			return false;
@@ -1877,7 +1877,7 @@ static bool chiptod_capp_check_tb_running(uint32_t chip_id)
 	return true;
 }
 
-bool chiptod_capp_timebase_sync(uint32_t chip_id)
+bool chiptod_capp_timebase_sync(uint32_t chip_id, uint32_t reg_offset)
 {
 	uint64_t tfmr;
 	uint64_t capp_tb;
@@ -1885,14 +1885,14 @@ bool chiptod_capp_timebase_sync(uint32_t chip_id)
 	unsigned int retry = 0;
 
 	/* Set CAPP TFMR to base tfmr value */
-	xscom_write(chip_id, CAPP_TFMR, base_tfmr);
+	xscom_write(chip_id, CAPP_TFMR + reg_offset, base_tfmr);
 
 	/* Reset CAPP TB errors before attempting the sync */
-	if (!chiptod_capp_reset_tb_errors(chip_id))
+	if (!chiptod_capp_reset_tb_errors(chip_id, reg_offset))
 		return false;
 
 	/* Switch CAPP TB to "Not Set" state */
-	if (!chiptod_capp_mod_tb(chip_id))
+	if (!chiptod_capp_mod_tb(chip_id, reg_offset))
 		return false;
 
 	/* Sync CAPP TB with core TB, retry while difference > 16usecs */
@@ -1904,19 +1904,19 @@ bool chiptod_capp_timebase_sync(uint32_t chip_id)
 
 		/* Make CAPP ready to get the TB, wait for chip sync */
 		tfmr = base_tfmr | SPR_TFMR_MOVE_CHIP_TOD_TO_TB;
-		xscom_write(chip_id, CAPP_TFMR, tfmr);
+		xscom_write(chip_id, CAPP_TFMR + reg_offset, tfmr);
 		if (!chiptod_wait_for_chip_sync())
 			return false;
 
 		/* Set CAPP TB from core TB */
-		xscom_write(chip_id, CAPP_TB, mftb());
+		xscom_write(chip_id, CAPP_TB + reg_offset, mftb());
 
 		/* Wait for CAPP TFMR tb_valid bit */
-		if (!chiptod_capp_check_tb_running(chip_id))
+		if (!chiptod_capp_check_tb_running(chip_id, reg_offset))
 			return false;
 
 		/* Read CAPP TB, read core TB, compare */
-		xscom_read(chip_id, CAPP_TB, &capp_tb);
+		xscom_read(chip_id, CAPP_TB + reg_offset, &capp_tb);
 		delta = mftb() - capp_tb;
 		if (delta < 0)
 			delta = -delta;
diff --git a/hw/phb3.c b/hw/phb3.c
index 30088c5..76fa1cc 100644
--- a/hw/phb3.c
+++ b/hw/phb3.c
@@ -3515,7 +3515,7 @@ static int64_t phb3_set_capi_mode(struct phb *phb, uint64_t mode,
 
 	phb3_init_capp_regs(p);
 
-	if (!chiptod_capp_timebase_sync(p->chip_id)) {
+	if (!chiptod_capp_timebase_sync(p->chip_id, reg_offset)) {
 		PHBERR(p, "CAPP: Failed to sync timebase\n");
 		return OPAL_HARDWARE;
 	}
diff --git a/include/chiptod.h b/include/chiptod.h
index daf37b1..b5dd2eb 100644
--- a/include/chiptod.h
+++ b/include/chiptod.h
@@ -32,6 +32,6 @@ extern bool chiptod_wakeup_resync(void);
 extern int chiptod_recover_tb_errors(void);
 extern void chiptod_reset_tb(void);
 extern bool chiptod_adjust_topology(enum chiptod_topology topo, bool enable);
-extern bool chiptod_capp_timebase_sync(uint32_t chip_id);
+extern bool chiptod_capp_timebase_sync(uint32_t chip_id, uint32_t reg_offset);
 
 #endif /* __CHIPTOD_H */
-- 
2.1.0