[Skiboot] [PATCH 2/2] hw/phb3: Ensure PQ bits are cleared in the IVC when masking IRQ
andrew.donnellan at au1.ibm.com
Tue Apr 26 09:56:03 AEST 2016
On 11/02/16 15:25, Michael Neuling wrote:
> When we mask an interrupt, we may race with another interrupt coming
> in from the hardware. If this occurs, the P and/or Q bit may end up
> being set but we never EOI/clear them. This could result in a lost
> interrupt or the next interrupt that comes in after re-enabling never
> being presented.
> This patch ensures that when masking an interrupt, any pending P/Q
> bits are cleared.
> This fixes a bug seen with some CAPI workloads which have lots of
> interrupt masking at the same time as high interrupt load. The fix is
> not specific to CAPI though.
> Signed-off-by: Michael Neuling <mikey at neuling.org>
Tested with an IBM internal CAPI accelerator that hit this issue.
Tested-by: Andrew Donnellan <andrew.donnellan at au1.ibm.com>
Andrew Donnellan OzLabs, ADL Canberra
andrew.donnellan at au1.ibm.com IBM Australia Limited
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