[Skiboot] [PATCH] PHB3: Fix unexpected ER (all) on errinjct by PCI config

Stewart Smith stewart at linux.vnet.ibm.com
Wed Oct 7 18:05:31 AEDT 2015

Gavin Shan <gwshan at linux.vnet.ibm.com> writes:
> This issue was found on SRIOV VFs initially and then I checked
> with Chad Larson who put much efforts to sort it out. As more
> experiments I did, the issue isn't limited to SRIOV VFs. That
> means the isue can be seen on non-SRIOV adapter as well: Firstly,
> I ensure that outbound request discard interrupt (bit#12) is
> enabled in PCI Express Port Interrupt Enable Register (offset:
> 0x558). Then injecting error to root complex by PAPR Error
> Injection Registers with PCI config read. Eventually, all (256)
> PEs are frozen. After clearing the bit, the target PE#0 is frozen
> as expected. As Chad pointed, the interrupt ("outbound request
> discard") is always raised during the error injection, which is
> translated to UTL's primary interrupt to freeze all (256) PEs.
> This drops bit#12 of PCI Express Port Interrupt Enable Register
> to avoid the UTL's primary interrupt caused by outbound request
> discard, in order to avoid freezing all (256) PEs during error
> injection via PCI config read.


merged at 2bb9c4bb257fe67f00a578cdd1bc41b6270ea27d into master.

Something that's certainly a candidate for stable I think, I'd like to
wait for outcome of other testing on (insert IBM internal bug number
here) so we can get a better complete explanation of what's being fixed,
and then we can cherry-pick.


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