[Skiboot] [PATCH 3/5] update users of GET/SETFIELD()
Dan Streetman
ddstreet at ieee.org
Wed Feb 18 07:38:52 AEDT 2015
The last two patches updated GETFIELD() and SETFIELD() to no longer
require the user to specify the mask and shift of a field, and to
remove all _LSH defines and rename any _MASK defines. There are
some places where the masks were used directly, where the caller
needs to have the _MASK suffix removed. There are also two users
of SETFIELD() where the field name still has the _MASK suffix
because there is an existing macro with the base name.
Change users of SETFIELD() to include the _MASK suffix where needed.
Change direct users of any mask to remove the _MASK suffix.
Signed-off-by: Dan Streetman <ddstreet at ieee.org>
---
hw/p5ioc2-phb.c | 2 +-
hw/p5ioc2.c | 2 +-
hw/p7ioc-phb.c | 8 ++++----
hw/p8-i2c.c | 2 +-
hw/phb3.c | 2 +-
hw/xscom.c | 14 +++++++-------
6 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/hw/p5ioc2-phb.c b/hw/p5ioc2-phb.c
index 0dcf0ce..91921b1 100644
--- a/hw/p5ioc2-phb.c
+++ b/hw/p5ioc2-phb.c
@@ -888,7 +888,7 @@ static void p5ioc2_phb_hwinit(struct p5ioc2_phb *p)
out_be32(p->ca_regs + CA_PHBIDn(p->index), phbid);
/* Set BUID */
- out_be32(p->regs + CAP_BUID, SETFIELD(CAP_BUID, 0,
+ out_be32(p->regs + CAP_BUID, SETFIELD(CAP_BUID_MASK, 0,
P7_BUID_BASE(p->buid)));
out_be32(p->regs + CAP_MSIBASE, P7_BUID_BASE(p->buid) << 16);
diff --git a/hw/p5ioc2.c b/hw/p5ioc2.c
index d8b9591..eb35e29 100644
--- a/hw/p5ioc2.c
+++ b/hw/p5ioc2.c
@@ -160,7 +160,7 @@ static void p5ioc2_ca_init(struct p5ioc2 *ioc, int ca)
printf("P5IOC2: Initializing Calgary %d...\n", ca);
/* Setup device BUID */
- val = SETFIELD(CA_DEVBUID, 0ul, ca ? P5IOC2_CA1_BUID : P5IOC2_CA0_BUID);
+ val = SETFIELD(CA_DEVBUID_MASK, 0ul, ca ? P5IOC2_CA1_BUID : P5IOC2_CA0_BUID);
out_be32(regs + CA_DEVBUID, val);
/* Setup HubID in TARm (and keep TCE clear, Linux will init that)
diff --git a/hw/p7ioc-phb.c b/hw/p7ioc-phb.c
index 99528f5..3f24767 100644
--- a/hw/p7ioc-phb.c
+++ b/hw/p7ioc-phb.c
@@ -1391,7 +1391,7 @@ static int64_t p7ioc_err_inject_mem32(struct p7ioc_phb *p, uint32_t pe_no,
/* Specified address is out of range */
if (!a) {
a = prefer;
- m = PHB_PAPR_ERR_INJ_MASK_MMIO_MASK;
+ m = PHB_PAPR_ERR_INJ_MASK_MMIO;
} else {
m = mask;
}
@@ -1436,7 +1436,7 @@ static int64_t p7ioc_err_inject_io32(struct p7ioc_phb *p, uint32_t pe_no,
/* Specified address is out of range */
if (!a) {
a = prefer;
- m = PHB_PAPR_ERR_INJ_MASK_IO_MASK;
+ m = PHB_PAPR_ERR_INJ_MASK_IO;
} else {
m = mask;
}
@@ -1467,7 +1467,7 @@ static int64_t p7ioc_err_inject_cfg(struct p7ioc_phb *p, uint32_t pe_no,
base = GETFIELD(IODA_PELTM_BUS, p->peltm_cache[pe_no]);
base &= (0xff - (((1 << (7 - v_bits)) - 1)));
a = SETFIELD(PHB_PAPR_ERR_INJ_MASK_CFG, 0x0ul, base);
- m = PHB_PAPR_ERR_INJ_MASK_CFG_MASK;
+ m = PHB_PAPR_ERR_INJ_MASK_CFG;
bus_no = GETFIELD(PHB_PAPR_ERR_INJ_MASK_CFG, addr);
bus_no &= (0xff - (((1 << (7 - v_bits)) - 1)));
@@ -1498,7 +1498,7 @@ static int64_t p7ioc_err_inject_dma(struct p7ioc_phb *p, uint32_t pe_no,
continue;
addr = SETFIELD(PHB_PAPR_ERR_INJ_MASK_DMA, 0ul, index);
- mask = PHB_PAPR_ERR_INJ_MASK_DMA_MASK;
+ mask = PHB_PAPR_ERR_INJ_MASK_DMA;
break;
}
diff --git a/hw/p8-i2c.c b/hw/p8-i2c.c
index 7ae0099..0f4c8af 100644
--- a/hw/p8-i2c.c
+++ b/hw/p8-i2c.c
@@ -704,7 +704,7 @@ static void p8_i2c_check_status(struct p8_i2c_master *master)
/* Mask the interrupts for this engine */
rc = xscom_write(master->chip_id, master->xscom_base + I2C_INTR_REG,
- ~I2C_INTR_ALL_MASK);
+ ~I2C_INTR_ALL);
if (rc) {
log_simple_error(&e_info(OPAL_RC_I2C_TRANSFER), "I2C: Failed "
"to disable the interrupts\n");
diff --git a/hw/phb3.c b/hw/phb3.c
index b27bac3..f7bacf1 100644
--- a/hw/phb3.c
+++ b/hw/phb3.c
@@ -2773,7 +2773,7 @@ static int64_t phb3_err_inject_cfg(struct phb3 *p, uint32_t pe_no,
/* Specified address is out of range */
if (a == 0xffffull) {
a = prefer;
- m = PHB_PAPR_ERR_INJ_MASK_CFG_MASK;
+ m = PHB_PAPR_ERR_INJ_MASK_CFG;
} else {
m = mask;
}
diff --git a/hw/xscom.c b/hw/xscom.c
index 471d057..e9861d7 100644
--- a/hw/xscom.c
+++ b/hw/xscom.c
@@ -27,7 +27,7 @@
/* Mask of bits to clear in HMER before an access */
#define HMER_CLR_MASK (~(SPR_HMER_XSCOM_FAIL | \
SPR_HMER_XSCOM_DONE | \
- SPR_HMER_XSCOM_STATUS_MASK))
+ SPR_HMER_XSCOM_STATUS))
#define XSCOM_ADDR_IND_FLAG PPC_BIT(0)
#define XSCOM_ADDR_IND_ADDR PPC_BITMASK(12,31)
@@ -259,7 +259,7 @@ static int xscom_indirect_read(uint32_t gcid, uint64_t pcb_addr, uint64_t *val)
/* Write indirect address */
addr = pcb_addr & 0x7fffffff;
data = XSCOM_DATA_IND_READ |
- (pcb_addr & XSCOM_ADDR_IND_ADDR_MASK);
+ (pcb_addr & XSCOM_ADDR_IND_ADDR);
rc = __xscom_write(gcid, addr, data);
if (rc)
goto bail;
@@ -270,8 +270,8 @@ static int xscom_indirect_read(uint32_t gcid, uint64_t pcb_addr, uint64_t *val)
if (rc)
goto bail;
if ((data & XSCOM_DATA_IND_COMPLETE) &&
- ((data & XSCOM_DATA_IND_ERR_MASK) == 0)) {
- *val = data & XSCOM_DATA_IND_DATA_MSK;
+ ((data & XSCOM_DATA_IND_ERR) == 0)) {
+ *val = data & XSCOM_DATA_IND_DATA;
break;
}
if ((data & XSCOM_DATA_IND_COMPLETE) ||
@@ -299,8 +299,8 @@ static int xscom_indirect_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val)
/* Write indirect address & data */
addr = pcb_addr & 0x7fffffff;
- data = pcb_addr & XSCOM_ADDR_IND_ADDR_MASK;
- data |= val & XSCOM_ADDR_IND_DATA_MSK;
+ data = pcb_addr & XSCOM_ADDR_IND_ADDR;
+ data |= val & XSCOM_ADDR_IND_DATA;
rc = __xscom_write(gcid, addr, data);
if (rc)
@@ -312,7 +312,7 @@ static int xscom_indirect_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val)
if (rc)
goto bail;
if ((data & XSCOM_DATA_IND_COMPLETE) &&
- ((data & XSCOM_DATA_IND_ERR_MASK) == 0))
+ ((data & XSCOM_DATA_IND_ERR) == 0))
break;
if ((data & XSCOM_DATA_IND_COMPLETE) ||
(retries >= XSCOM_IND_MAX_RETRIES)) {
--
1.8.3.1
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