[Pdbg] [PATCH 01/10] libpdbg/p9chip.c: disable ramming LSU opcodes

[Nicholas Piggin]

On Tue, 08 May 2018 12:05:00 +1000
Alistair Popple <alistair at popple.id.au> wrote:

> On Thursday, 3 May 2018 4:26:53 PM AEST Nicholas Piggin wrote:
> > These are too easy to cause checkstops, and there's a better
> > alternative.
> > 
> > Signed-off-by: Nicholas Piggin <npiggin at gmail.com>
> > ---
> >  libpdbg/p9chip.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/libpdbg/p9chip.c b/libpdbg/p9chip.c
> > index 97456a8..339d2f0 100644
> > --- a/libpdbg/p9chip.c
> > +++ b/libpdbg/p9chip.c
> > @@ -309,6 +309,11 @@ out:
> >  
> >  static int p9_ram_instruction(struct thread *thread, uint64_t opcode, uint64_t *scratch)
> >  {
> > +	if ((opcode & OPCODE_MASK) == LD_OPCODE) {
> > +		printf("RAM LSU opcodes are disabled for POWER9 because exceptions will checkstop. Use ADU instead.\n");  
> 
> On P8 these were used as an easy way to do address translation (EA -> RA) by
> getting the core to do the translation as exceptions didn't checkstop. However I
> agree we should just disable it on P9 if checkstops cause exceptions. Thanks!

Ahh right, I didn't know that. Possibly that was done because the radix MMU mode
interacts with MSR[HV] which ramming sets, which would change the way xlates are
done.

> To use the ADU in the same way though we'd need to implement something to walk
> the page tables.

Yes, we could do the full hash and radix walks, because we can get all registers
and even SLB with ramming. That will be a big job to get all hash cases correct,
but radix should be quite do-able, and then you could start with just the cases
that are important for Linux powernv, etc.

Thanks,
Nick