[OpenPower-Firmware] [EXTERNAL] Re: Hardware documentation

[Marty E. Plummer]

On Tue, Oct 29, 2019 at 12:13:51PM -0600, Daniel M Crowell wrote:
> 
> The SBE determines the logical memory address that the bootloader gets
> loaded into, that is the HRMOR.  There are some explicit operations done to
> preload these addresses into the cache at the expected address.  Depending
> on your box and code level, Hostboot starts at 128MB or 4GB-256MB.  The
> bootloader actually runs at +2MB from where Hostboot eventually gets
> started at, so you end up with this:
> 	128 MB = Hostboot
> 	129 MB = HBB with ECC (pulled from PNOR)
> 	130 MB = Bootloader
> 	131 MB = HBB without ECC (used for secureboot verification)
> Note that HRMOR=130M during bootloader and it switches to 128M for
> Hostboot.
> 
Sorry for rezzing an old thread, but would like a bit more info on this.
So, bootloader runs at 130mb hrmor, and jumps to 128mb hrmor for
hostboot proper? Or does the hrmor remain at 128mb for this entire block
of code and bootloader is just loaded at +2MB past it?

What is hrmor like when skiboot gets loaded?
> > In coreboot terminology bootblock and romstage will run out of the cache,
> > and romstage will init the ram enough to load ramstage into it.
> We don't really divide between cache and cache+memory with regards to our
> code load.  Our division is based on code being pageable (HBI) versus not
> (HBB).  We require a lot of code from HBI to get mainstore memory online.
> 
Gotcha, assume 'mainstore memory' means actual dram?
> --
> Dan Crowell
> Senior Software Engineer - Power Systems Enablement Firmware
> IBM Rochester: t/l 553-2987
> dcrowell at us.ibm.com
>