[OpenPower-Firmware] SRESET and idle CPU

[Stewart Smith]

On Tue, Jul 28, 2020, at 7:29 AM, Artem Senichev wrote:
> As it turns out, the pdbg solution works fine, but it depends on the 
> interval between 'stop' and 'sreset'.
> When this pause is longer than 1 second, the chance of sreset being 
> processed becomes significantly less.

It's plausible that neither stop nor sreset waits for the core to get into the right state. The skiboot direct_controls.c probably does though.