[OpenPower-Firmware] SRESET and idle CPU

Stewart Smith stewart at flamingspork.com
Wed Jul 29 11:20:59 AEST 2020


On Mon, Jul 27, 2020, at 6:56 AM, Artem Senichev wrote:
> Excuse me, I am not an expert in POWER CPU architecture. What is the STOP5?
> I found some mentions about this state in skiboot and it somehow related to
> CPU idle, but I still don't see the whole picture.

It's the first stop state that powers off the core.


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