[OpenPower-Firmware] SBE questions

[Dean Sanner]

> Ok, cool. strangely enough my dumped seeprom has a different address, I
> suppose that is due to being the talos firmware rather upstream, but the
> entry point is __pk_boot which is deep under the imports dir.

Yeah, the address will be different with each built image

> Oh, I was under the impression that hbbl was run on the sbe using that
> modified power core. This is still BE code, correct? Another question
> then, could you point out where the sbe firmware->hbbl handoff happens,
> then? I'm mostly interested in the ppe42->p9 execution switch happens.

The switch happens in istep 5.1 and 5.2:

5.1: loads the HBBL image from SEEPROM into P9 core cache (as memory)
In src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C,
Function is p9_sbe_load_bootloader.  Called by
src/sbefw/app/power/ipl_table.C.  In there you can see the SBE getting
the .hbbl section and then passing it into the HWP (stuff in import).
The HWP when uses a unit called the PBA to push 128 byte chunks of
data from the SEEPROM into the P9 cache.

5.2:starts instructions on the P9 core:
In src/sbefw/app/power/ipl_table.C it calls istepStartInstruction with
the function pointer of p9_sbe_instruct_start, which simply kicks thread
0 on the master core to "go".   At this point the SBE enters its
"runtime" state where it just listens for external chipOPs (either
BMC or Hostboot) to trigger it to do services for them.

The HBBL takes over the rest of the IPL flow.  In the hostboot repo
you can look at src/bootloader/bl_start.S src/bootloader/bootloader.C.
in main() this is where it starts to access the PNOR searching FFS
for the HBB partition.

bl_pnorAccess::getHBBSection(g_blData->blToHbData.lpcBAR,
                                     g_blData->bl_hbbSection,
                                     l_errCode,
                                     l_pnorStart);
> >
> > Unless you want to run coreboot _from_ the SBE (limited environment and
I
> Not coreboot proper per se. The primary thing wrt modifying the sbe
> itself is (imo) c++ in this low-level firmware is really difficult to
> track as compared to plain c/assembly.

I can understand that.  Something to keep in mind if you pursue this --
the is that future IBM chip support is really reliant on the HW
procedure framework (FAPI2) -- so if you can make the stuff in
src/import slide in easily that would help long term (tho it would
probably cause more pain short term).

Alistair has some thoughts on various improvements to the FAPI2 stuff,
copying him if you are interested.

> > don't see
> > the value?)  I would recommend focusing on modifications to the
Hostboot
> > bootloader.
> Yeah, with this information I think I can hook in at the hbbl stage so I
> don't have to rewrite everything from the ground up.

Agreed

Dean Sanner
dsanner at us.ibm.com
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