<html><body><p><tt><font size="2">> Ok, cool. strangely enough my dumped seeprom has a different address, I<br>> suppose that is due to being the talos firmware rather upstream, but the<br>> entry point is __pk_boot which is deep under the imports dir.<br></font></tt><br><tt><font size="2">Yeah, the address will be different with each built image</font></tt><br><br><tt><font size="2">> Oh, I was under the impression that hbbl was run on the sbe using that<br>> modified power core. This is still BE code, correct? Another question<br>> then, could you point out where the sbe firmware->hbbl handoff happens,<br>> then? I'm mostly interested in the ppe42->p9 execution switch happens.<br></font></tt><br><tt><font size="2">The switch happens in istep 5.1 and 5.2:</font></tt><br><br><tt><font size="2">5.1: loads the HBBL image from SEEPROM into P9 core cache (as memory)</font></tt><br><tt><font size="2">In </font></tt><tt><font size="2">src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C, </font></tt><br><tt><font size="2">Function is p9_sbe_load_bootloader. Called by </font></tt><br><tt><font size="2">src/sbefw/app/power/ipl_table.C. In there you can see the SBE getting</font></tt><br><tt><font size="2">the .hbbl section and then passing it into the HWP (stuff in import).</font></tt><br><tt><font size="2">The HWP when uses a unit called the PBA to push 128 byte chunks of</font></tt><br><tt><font size="2">data from the SEEPROM into the P9 cache.</font></tt><br><br><tt><font size="2">5.2:starts instructions on the P9 core:</font></tt><br><tt><font size="2">In src/sbefw/app/power/ipl_table.C it calls istepStartInstruction with</font></tt><br><tt><font size="2">the function pointer of p9_sbe_instruct_start, which simply kicks thread</font></tt><br><tt><font size="2">0 on the master core to "go". At this point the SBE enters its </font></tt><br><tt><font size="2">"runtime" state where it just listens for external chipOPs (either</font></tt><br><tt><font size="2">BMC or Hostboot) to trigger it to do services for them.</font></tt><br><br><tt><font size="2">The HBBL takes over the rest of the IPL flow. In the hostboot repo</font></tt><br><tt><font size="2">you can look at </font></tt><tt><font size="2">src/bootloader/bl_start.S src/bootloader/bootloader.C.</font></tt><br><tt><font size="2">in main() this is where it starts to access the PNOR searching FFS</font></tt><br><tt><font size="2">for the HBB partition.<br></font></tt><br><tt><font size="2">bl_pnorAccess::getHBBSection(g_blData->blToHbData.lpcBAR,</font></tt><br><tt><font size="2"> g_blData->bl_hbbSection,</font></tt><br><tt><font size="2"> l_errCode,</font></tt><br><tt><font size="2"> l_pnorStart);</font></tt><br><tt><font size="2">> > <br>> > Unless you want to run coreboot _from_ the SBE (limited environment and I<br>> Not coreboot proper per se. The primary thing wrt modifying the sbe<br>> itself is (imo) c++ in this low-level firmware is really difficult to<br>> track as compared to plain c/assembly.<br></font></tt><br><tt><font size="2">I can understand that. Something to keep in mind if you pursue this --</font></tt><br><tt><font size="2">the is that future IBM chip support is really reliant on the HW </font></tt><br><tt><font size="2">procedure framework (FAPI2) -- so if you can make the stuff in </font></tt><br><tt><font size="2">src/import slide in easily that would help long term (tho it would</font></tt><br><tt><font size="2">probably cause more pain short term). </font></tt><br><br><tt><font size="2">Alistair has some thoughts on various improvements to the FAPI2 stuff,</font></tt><br><tt><font size="2">copying him if you are interested.</font></tt><br><br><tt><font size="2">> > don't see<br>> > the value?) I would recommend focusing on modifications to the Hostboot<br>> > bootloader.<br>> Yeah, with this information I think I can hook in at the hbbl stage so I<br>> don't have to rewrite everything from the ground up.<br></font></tt><br><tt><font size="2">Agreed</font></tt><br><br><font size="2">Dean Sanner<br>dsanner@us.ibm.com<br></font><BR>
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