Kestrel soft BMC

[Timothy Pearson]

I'd like to call attention to a project we just released here at Raptor Engineering: the Kestrel POWER-based soft BMC.  This has been in the works for a while now, and if all goes as planned could be a potential (slow) OpenBMC target later this year.

Kestrel is designed for openness and security; it has been developed and is supported exclusively using open FPGA tooling (Yosys/NextPNR/OpenOCD) running on open-ISA OpenPOWER systems [1] and targeting the Lattice ECP5 series of FPGAs.  It implements all of the basic functions required to IPL a POWER host (FSI, SPI, LPC, I2C, VUART, etc.), and is currently able to IPL a Blackbird system without any involvement of the ASpeed integrated BMC.

The main project README is available at https://gitlab.raptorengineering.com/kestrel-collaboration/kestrel-litex/litex-boards/-/blob/master/README.md and there are also build instructions at https://gitlab.raptorengineering.com/kestrel-collaboration/kestrel-litex/litex/-/wikis/Quick-Start .  Contributors are welcome, though we suspect many on this list may wait to contribute until we have at least basic Linux support up for the Kestrel system.

As a side note, we have hardware coming down the line around midyear that will allow us to expand Kestrel with network functionality and additional features.  This hardware will likely be made available for public purchase around that time as well.

Enjoy!

--
Timothy Pearson
Raptor Engineering, LLC

[1] To be specific, most development occurs on Blackbird desktops with some Talos II servers in the mix.  At no point in the development / build / test process are any proprietary tools or x86 processors involved.