[PATCH v3 3/4] soc: aspeed: Add eSPI driver

[ChiaWei Wang]

> From: Joel Stanley <joel at jms.id.au>
> Sent: Friday, August 27, 2021 1:49 PM
> 
> On Fri, 27 Aug 2021 at 03:52, ChiaWei Wang
> <chiawei_wang at aspeedtech.com> wrote:
> >
> > Aspeed 5th and 6th generation SoCs are based on the ARM 32-bits
> architecture.
> > Should we follow the report to make the driver 64-bits compatible?
> > Or revise the driver to use more specific data types?
> 
> Yes, in general it's expected your driver will compile cleanly for 64-bit
> architectures. This helps with testing and static analysis, where CI builds all the
> drivers for x86.

Understood. Will fix the data type issue in the next submission.
Thanks.

Chiawei