How to use eSPI between Host and slave BMC in openbmc project

zhang_cy1989 zhang_cy1989 at
Fri May 15 23:43:28 AEST 2020

Dear James/andrew/Oskar
    Thanks a lot.
    I am studying eSPI spec. But it's hard to find any products with eSPI.
    Your reply gives more understanding about eSPI.
    Looking forward to more applications with eSPI in openbmc project.
    Thanks again.

| |
zhang_cy1989 at
On 5/11/2020 21:31,Oskar Senft<osk at> wrote:

Jeremy's response matches my understanding, thank you!

> 1 Are there some solutions to use eSPI interface in openbmc project?

There are some platforms in development that use eSPI between the host
and BMC, yes.

On platforms using Intel's C620 series PCH + AST2500 BMC,  eSPI can be used basically exactly like LPC on both sides.
For the BMC, we need some support in the kernel to handle eSPI
behaviour. There is a prototype driver for the ast2500 eSPI slave
around, but it hasn't made it upstream:
Yes, without that, the PCH will not release the host CPU from reset.

 > 5 eSPI interface can transmit io cycle and mem cycle, 
> but in which case or applications eSPI transfer mem cycle?

I haven't seen anything specific, I don't think it'd be too useful in
our architecture.

I've seen platforms that load the "lower 16 MiB" from SPI flash (descriptor region, ME, GbE FW) and load the "upper 16 MiB" (the actual BIOS) via LPC. The same should be possible via eSPI.

Note that with eSPI it would "technically" be possible to load _ALL_ FW for the PCH (descriptor region, ME, GbE FW, BIOS) via eSPI using the "Slave Attached Flash Sharing" (SAFS) feature. However, there's no BMC available today that I know of that supports that, but support is in the works on BMC chips. Having said that, Intel's support for SAFS is unclear: some documents claim it's supported, others state it's not POR (SAFS that is).

Happy to provide more information.

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <>

More information about the openbmc mailing list