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<span>Dear James/andrew/Oskar
</span></div><div> Thanks a lot.</div><div> I am studying e<font size="2" style="font-size: 14px;">SPI spec. But <span style="orphans: 2; widows: 2;">it's hard to find any products with eSPI.</span></font></div><div> Your reply gives more understanding about eSPI.</div><div> </div><div><font size="2"><span style="font-size: 14px;"> </span></font><span style="orphans: 2; widows: 2;"><font size="2" style="font-size: 14px;"><span style="font-size: 14px;">Looking forward to more ap</span>plications</font></span><span style="orphans: 2; widows: 2;"><font size="2" style="font-size: 14px;"> with eSPI in openbmc project.</font></span></div><div style="orphans: 2; widows: 2; "> Thanks again.</div><div style="orphans: 2; widows: 2; ">BR</div><div style="orphans: 2; widows: 2; ">Felix</div><div> </div>
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<div style="font-size:12px;line-height:1.5;word-break:break-all;margin-left:10px;margin-right:10px">On <span class="mail-date">5/11/2020 21:31</span>，<a class="mail-to" style="text-decoration:none;color:#2a83f2;" href="mailto:osk@google.com">Oskar Senft<osk@google.com></a> wrote： </div>
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<blockquote id="ntes-pcmail-quote" style="margin: 0; padding: 0; font-size: 14px; font-family: '微软雅黑';">
<div dir="ltr"><div>Hi</div><div><br></div><div>Jeremy's response matches my understanding, thank you!</div><div><br></div><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">> 1 Are there some solutions to use eSPI interface in openbmc project?<br>
<br>
There are some platforms in development that use eSPI between the host<br>
and BMC, yes.<br></blockquote><div>On platforms using Intel's C620 series PCH + AST2500 BMC, eSPI can be used basically exactly like LPC on both sides.</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">For the BMC, we need some support in the kernel to handle eSPI<br>
behaviour. There is a prototype driver for the ast2500 eSPI slave<br>
around, but it hasn't made it upstream:<br>
<br>
<a href="https://lists.ozlabs.org/pipermail/openbmc/2018-February/010937.html" rel="noreferrer" target="_blank">https://lists.ozlabs.org/pipermail/openbmc/2018-February/010937.html</a></blockquote><div>Yes, without that, the PCH will not release the host CPU from reset.</div><div><br></div><div> > 5 eSPI interface can transmit io cycle and mem cycle， </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
> but in which case or applications eSPI transfer mem cycle?<br>
<br>
I haven't seen anything specific, I don't think it'd be too useful in<br>
our architecture.<br></blockquote><div>I've seen platforms that load the "lower 16 MiB" from SPI flash (descriptor region, ME, GbE FW) and load the "upper 16 MiB" (the actual BIOS) via LPC. The same should be possible via eSPI.</div><div><br></div><div>Note that with eSPI it would "technically" be possible to load _ALL_ FW for the PCH (descriptor region, ME, GbE FW, BIOS) via eSPI using the "Slave Attached Flash Sharing" (SAFS) feature. However, there's no BMC available today that I know of that supports that, but support is in the works on BMC chips. Having said that, Intel's support for SAFS is unclear: some documents claim it's supported, others state it's not POR (SAFS that is).</div><div><br></div><div>Happy to provide more information.</div><div><br></div><div>Oskar.</div></div></div>
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