[PATCH v4 0/5] Remove LPC register partitioning

Chia-Wei, Wang chiawei_wang at aspeedtech.com
Tue Dec 29 17:31:52 AEDT 2020

The LPC controller has no concept of the BMC and the Host partitions.
The incorrect partitioning can impose unnecessary range restrictions
on register access through the syscon regmap interface.

For instance, HICRB contains the I/O port address configuration
of KCS channel 1/2. However, the KCS#1/#2 drivers cannot access
HICRB as it is located at the other LPC partition.

In addition, to be backward compatible, the newly added HW control
bits could be located at any reserved bits over the LPC addressing

Thereby, this patch series aims to remove the LPC partitioning for
better driver development and maintenance. This requires the change
to both the device tree and the driver implementation. To ensure
both sides are synchronously updated, a v2 binding check is added.

Chagnes since v3:
	- Revise binding check as suggested by Haiyue Wang

Changes since v2:
	- Add v2 binding check to ensure the synchronization between the
	  device tree change and the driver register offset fix.

Changes since v1:
	- Add the fix to the aspeed-lpc binding documentation.

Chia-Wei, Wang (5):
  dt-bindings: aspeed-lpc: Remove LPC partitioning
  ARM: dts: Remove LPC BMC and Host partitions
  ipmi: kcs: aspeed: Adapt to new LPC DTS layout
  pinctrl: aspeed-g5: Adapt to new LPC device tree layout
  soc: aspeed: Adapt to new LPC device tree layout

 .../devicetree/bindings/mfd/aspeed-lpc.txt    |  99 +++----------
 arch/arm/boot/dts/aspeed-g4.dtsi              |  74 ++++------
 arch/arm/boot/dts/aspeed-g5.dtsi              | 135 ++++++++----------
 arch/arm/boot/dts/aspeed-g6.dtsi              | 135 ++++++++----------
 drivers/char/ipmi/kcs_bmc_aspeed.c            |  27 ++--
 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c    |  17 ++-
 drivers/soc/aspeed/aspeed-lpc-ctrl.c          |  20 ++-
 drivers/soc/aspeed/aspeed-lpc-snoop.c         |  23 +--
 8 files changed, 225 insertions(+), 305 deletions(-)


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