[PATCH linux dev-5.3] ARM: dts: aspeed: tacoma: Disable CS1 as it is broken

[Cédric Le Goater]

On 26/09/2019 11:33, Joel Stanley wrote:
> We currently hang when attempting to probe the second flash chip on the
> FMC. Disable it until this issue is resolved.


Reviewed-by: Cédric Le Goater <clg at kaod.org>


Below is a fix. It's worth a try.

Thanks,

C. 

>From cb1237b2fdf8f5a55254ac066d8ab3c4924c93b6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg at kaod.org>
Date: Thu, 26 Sep 2019 15:45:37 +0200
Subject: [PATCH] mtd: spi-nor: aspeed: fix training of multiple CS on the
 AST2600
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Each CE has its own read timing compensation register.

Signed-off-by: Cédric Le Goater <clg at kaod.org>
---
 drivers/mtd/spi-nor/aspeed-smc.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c
index e9bc89755912..9873824eb381 100644
--- a/drivers/mtd/spi-nor/aspeed-smc.c
+++ b/drivers/mtd/spi-nor/aspeed-smc.c
@@ -1133,7 +1133,7 @@ static int aspeed_smc_calibrate_reads_ast2600(struct aspeed_smc_chip *chip, u32
 		fread_timing_val |= hcycle << shift;
 
 		/* no DI input delay first  */
-		writel(fread_timing_val, controller->regs + info->timing);
+		writel(fread_timing_val, controller->regs + info->timing + chip->cs);
 		pass = aspeed_smc_check_reads(chip, golden_buf, test_buf);
 		dev_dbg(chip->nor.dev,
 			"  * [%08x] %d HCLK delay, DI delay none : %s",
@@ -1149,7 +1149,8 @@ static int aspeed_smc_calibrate_reads_ast2600(struct aspeed_smc_chip *chip, u32
 			fread_timing_val &= ~(0xf << (4 + shift));
 			fread_timing_val |= delay_ns << (4 + shift);
 
-			writel(fread_timing_val, controller->regs + info->timing);
+			writel(fread_timing_val,
+			       controller->regs + info->timing + chip->cs);
 			pass = aspeed_smc_check_reads(chip, golden_buf, test_buf);
 			dev_dbg(chip->nor.dev,
 				"  * [%08x] %d HCLK delay, DI delay %d.%dns : %s",
-- 
2.21.0