[PATCH linux dev-5.3 v2 3/8] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs

[Joel Stanley]

On Wed, 25 Sep 2019 at 15:34, Andrew Jeffery <andrew at aj.id.au> wrote:
>
> RCLK is a fixed 50MHz clock derived from HPLL that is described by a
> single gate for each MAC.
>
> Signed-off-by: Andrew Jeffery <andrew at aj.id.au>

Reviewed-by: Joel Stanley <joel at jms.id.au>

> ---
>  drivers/clk/clk-aspeed.c | 27 ++++++++++++++++++++++++++-
>  1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c
> index abf06fb6453e..9bd5155598d6 100644
> --- a/drivers/clk/clk-aspeed.c
> +++ b/drivers/clk/clk-aspeed.c
> @@ -14,7 +14,7 @@
>
>  #include "clk-aspeed.h"
>
> -#define ASPEED_NUM_CLKS                36
> +#define ASPEED_NUM_CLKS                38
>
>  #define ASPEED_RESET2_OFFSET   32
>
> @@ -28,6 +28,7 @@
>  #define  AST2400_HPLL_BYPASS_EN        BIT(17)
>  #define ASPEED_MISC_CTRL       0x2c
>  #define  UART_DIV13_EN         BIT(12)
> +#define ASPEED_MAC_CLK_DLY     0x48
>  #define ASPEED_STRAP           0x70
>  #define  CLKIN_25MHZ_EN                BIT(23)
>  #define  AST2400_CLK_SOURCE_SEL        BIT(18)
> @@ -462,6 +463,30 @@ static int aspeed_clk_probe(struct platform_device *pdev)
>                 return PTR_ERR(hw);
>         aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw;
>
> +       if (of_device_is_compatible(pdev->dev.of_node, "aspeed,ast2500-scu")) {
> +               /* RMII 50MHz RCLK */
> +               hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0,
> +                                               50000000);
> +               if (IS_ERR(hw))
> +                       return PTR_ERR(hw);
> +
> +               /* RMII1 50MHz (RCLK) output enable */
> +               hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
> +                               scu_base + ASPEED_MAC_CLK_DLY, 29, 0,
> +                               &aspeed_clk_lock);
> +               if (IS_ERR(hw))
> +                       return PTR_ERR(hw);
> +               aspeed_clk_data->hws[ASPEED_CLK_GATE_MAC1RCLK] = hw;
> +
> +               /* RMII2 50MHz (RCLK) output enable */
> +               hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
> +                               scu_base + ASPEED_MAC_CLK_DLY, 30, 0,
> +                               &aspeed_clk_lock);
> +               if (IS_ERR(hw))
> +                       return PTR_ERR(hw);
> +               aspeed_clk_data->hws[ASPEED_CLK_GATE_MAC2RCLK] = hw;
> +       }
> +
>         /* LPC Host (LHCLK) clock divider */
>         hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
>                         scu_base + ASPEED_CLK_SELECTION, 20, 3, 0,
> --
> 2.20.1
>