[PATCH linux dev-5.3 00/13] mtd: spi-nor: aspeed: add support for ast2600

[Cédric Le Goater]

Hello,

It is based on Brad Bishop series adding the Rainier system system.
The training is still experimental and optimistic. The algorithm might
need some more tuning when systems become available. Quad I/O support
is not implemented.

The Segment Register have a different layout on the AST2600 and the
AHB window of CS other than the first are closed. We will need support
from the firmware or the DT to activate multiple chips on the same
bus.

These driver extensions will not be pushed to mainline.

Thanks,

C.

Cédric Le Goater (13):
  ARM: dts: aspeed-g6: Add FMC and SPI devices
  ARM: dts: aspeed: rainier: Enable FMC and SPI devices
  ARM: dts: aspeed: rainier: Enable MAC0
  ARM: dts: ast2600-evb: Enable FMC and SPI devices
  mtd: spi-nor: Add support for w25q512jv
  mtd: spi-nor: aspeed: Introduce a field for the AHB physical address
  mtd: spi-nor: aspeed: Introduce segment operations
  mtd: spi-nor: aspeed: add initial support for ast2600
  mtd: spi-nor: aspeed: Check for disabled segments on the AST2600
  mtd: spi-nor: aspeed: Introduce training operations per platform
  mtd: spi-nor: aspeed: Introduce a HCLK mask for training
  mtd: spi-nor: aspeed: check upper freq limit when doing training
  mtd: spi-nor: aspeed: add support for AST2600 training

 drivers/mtd/spi-nor/aspeed-smc.c             | 283 ++++++++++++++++---
 drivers/mtd/spi-nor/spi-nor.c                |   2 +
 arch/arm/boot/dts/aspeed-ast2600-evb.dts     |  24 ++
 arch/arm/boot/dts/aspeed-bmc-opp-rainier.dts |  38 +++
 arch/arm/boot/dts/aspeed-g6.dtsi             |  79 ++++++
 5 files changed, 385 insertions(+), 41 deletions(-)

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2.21.0