[PATCH linux dev-5.2 v2 3/4] ARM: dts: Aspeed: ast2600: Add I2C busses

Ryan Chen ryan_chen at aspeedtech.com
Thu Sep 19 10:34:40 AEST 2019


Hello,
	It is correct, the AST2600 IRQ number range is from GIC_SPI 110 ~125.

-----Original Message-----
From: openbmc [mailto:openbmc-bounces+ryan_chen=aspeedtech.com at lists.ozlabs.org] On Behalf Of Cedric Le Goater
Sent: Thursday, September 19, 2019 1:02 AM
To: Eddie James <eajames at linux.ibm.com>; openbmc at lists.ozlabs.org
Cc: andrew at aj.id.au
Subject: Re: [PATCH linux dev-5.2 v2 3/4] ARM: dts: Aspeed: ast2600: Add I2C busses

On 18/09/2019 17:57, Cédric Le Goater wrote:
> On 18/09/2019 16:53, Eddie James wrote:
>>
>> On 9/18/19 5:18 AM, Cédric Le Goater wrote:
>>> On 13/09/2019 18:15, Eddie James wrote:
>>>> Add all the I2C busses to the AST2600 dtsi and set their required 
>>>> properties.
>>>>
>>> The DT defines an interrupt per I2C bus but this is not how the I2C 
>>> driver operates. It still uses the old mode from the Aspeed AST2500.
>>
>>
>> Oh? The I2C interrupt controller driver is a separate driver, which I didn't include a node for in the AST2600 dts. As far as I can tell the I2C bus driver just asks for it's interrupt and uses it, so by setting each bus to it's GIC interrupt line (instead of the line from the I2C interrupt controller like in the AST2500), the I2C driver receives the correct interrupt.
> 
> ok. I am seeing this from the I2C model side and that is where the 
> problem must be. I will dig in QEMU.

We now have one irq per bus and the I2C model needs some rework for the AST2600 because we only had one with the previous Aspeed SoC.

Are you sure of the I2C IRQ number range ? Shouldn't we using range
142-157 instead ? 

Thanks,

C.


More information about the openbmc mailing list