[PATCH linux dev-5.3 v2 3/8] fsi: aspeed: Fix endian register to enable single byte reads

[Joel Stanley]

From: Andrew Jeffery <andrew at aj.id.au>

The endian register controls where the incoming bytes end up in the data
register. Currently reading single bytes is broken, and reading half
words is causes the data to appear in both the upper and lower part of
the register.

The current value of the OPB0 read order selection register caused a
data read register value of 0xffffffff to be read for single byte
accesses over FSI. A value of 0x03 for the read order byte-access slot
correctly "swaps" the BE MSB value to the LE LSB for extraction by the
APB2OPB bridge:

    # devmem 0x1e79b05c
    0x00030B1B
    # dd if=raw bs=1 count=1 | hexdump -C
        fsi_master_read: fsi0:00:00 00000000[1]
         opb read: addr a0000000 size 1: result ffffffc0 status: 00000000 irq_status: 00010000
         opb read: addr 800000d0 size 4: result 00000000 status: 00000002 irq_status: 00010000
         opb read: addr 800000d0 size 4: result 00000000 status: 00000002 irq_status: 00010000
         opb read: addr 800001d0 size 4: result 00000000 status: 00000002 irq_status: 00010000
         mresp0 00000000 mstap0 00000000 mesrb0 00000000
        fsi_master_rw_result: fsi0:00:00 00000000[1] => {c0} ret 0
    1+0 records in
    1+0 records out
    00000000  c0                                                |.|
    00000001

This fixes half-word access read order selection in the same manner.

Signed-off-by: Andrew Jeffery <andrew at aj.id.au>
Signed-off-by: Joel Stanley <joel at jms.id.au>
---
 drivers/fsi/fsi-master-aspeed.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/fsi/fsi-master-aspeed.c b/drivers/fsi/fsi-master-aspeed.c
index b520f5df567c..5b947c70c0f9 100644
--- a/drivers/fsi/fsi-master-aspeed.c
+++ b/drivers/fsi/fsi-master-aspeed.c
@@ -635,7 +635,7 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev)
 	writel(fsi_base, aspeed->base + OPB_FSI_BASE);
 
 	/* Set read data order */
-	writel(0x0011bb1b, aspeed->base + OPB0_R_ENDIAN);
+	writel(0x00030b1b, aspeed->base + OPB0_R_ENDIAN);
 
 	/* Set write data order */
 	writel(0x0011bb1b, aspeed->base + OPB0_W_ENDIAN);
-- 
2.24.0.rc1