[PATCH dev-5.0 v1] EDAC: Add Nuvoton NPCM7xx EDAC driver

[George Hung (洪忠敬)]

Dear Paul,

> First question, did you send this upstream already? See entry EDAC-CORE
> in `MAINTAINERS`.

No, I don't send it to upstream yet.

> 
> On 03/29/19 09:54, George Hung wrote:
> > Add support for the Nuvoton NPCM7xx SoC EDAC driver
> 
> Could you please add the datasheet name and version to the commit
> message.

OK, I will add the datasheet information to the commit message.

datasheet:
"Cadence DDR Controller User’s Manual For DDR3 & DDR4 Memories"

> Also, how did you test this?

The datasheet provide the forcing an ECC error event method:

Write a value to the xor_check_bits parameter that will trigger an ECC event
once that word is read.

For example, to force a single-bit correctable error on bit 0 of the user-word space shown,
write 0x75 into that byte of the xor_check_bits parameter.
(mem base: 0xf0824000, register: 0x178).

# devmem 0xf0824178 32 0x7501

To force a double-bit un-correctable error for the user-word space, write 0x03 into that
byte of the xor_check_bits parameter.

# devmem 0xf0824178 32 0x301

> 
> > Signed-off-by: George Hung <george.hung at quantatw.com>
> > ---
> >  .../bindings/edac/npcm7xx-sdram-edac.txt      |  17 +
> >  drivers/edac/Kconfig                          |   7 +
> >  drivers/edac/Makefile                         |   1 +
> >  drivers/edac/npcm7xx_edac.c                   | 424
> ++++++++++++++++++
> >  4 files changed, 449 insertions(+)
> >  create mode 100644
> Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt
> >  create mode 100644 drivers/edac/npcm7xx_edac.c
> 
> Could you please also add an entry to the file `MAINTAINERS`?

Yes, I will add the file, `MAINTAINERS` to the patch.

> 
> […]
> 
> 
> Kind regards,
> 
> Paul

BRs

George