How to configure Clock Stop Control Register

[Henbin Chang]

Hi Joel,

Thanks for your response.

But I don't understand why 'SCU0C[8] = 1' is related with
aspeed_lpc_ctrl_ioctl().

I don't see any code to write SCU0C register In the aspeed_lpc_ctrl_ioctl().

Update my finding.

I find the aspeed-lpc-ctrl driver can throw the below error message and
'return -ENODEV',
'Didn't find host pnor flash node'

After checking the my dts, it lacks of the 'flash' filed in the lpc_ctrl .

So I refer the aspeed-bmc-opp-zaius.dts and add it into my dts.
&lpc_ctrl {
    status = "okay";
    memory-region = <&flash_memory>;
    flash = <&spi1>;
};

And then the lpc aspeed-lpc-ctrl driver can be loaded successfully.
And the SCU0C[8] isn't set as 1b'.

For my understanding, the 'spi1' indicates the system SPI connected into
BIOS SPI flash.
I don't know why lpc_ctrl has to need the 'flash' field.

Thanks for your help.

2018-06-06 17:01 GMT+08:00 Joel Stanley <joel at jms.id.au>:

> Hello Henbin,
>
> tldr: you need to ensure mboxd has run so the aspeed-lpc-ctrl ioctl
> has been performed.
>
> See below for my explanation.
>
> On 6 June 2018 at 14:32, Henbin Chang <henbinchang at gmail.com> wrote:
> >> What kernel tree are you building/booting? Can you provide a link?
> >> Currently we've tied the LCLK to enabling LPC2AHB bridge:
> >>
> >> https://github.com/openbmc/linux/blob/dev-4.13/arch/arm/
> boot/dts/aspeed-g5.dtsi#L302
> >> You may need to add the following to your dts if you've developed your
> >> own:
> >> ```
> >> &lpc_ctrl {
> >>         status = "okay";
> >> };
> >
> > I use dev-4.13 branch (the last commit is
> > aca92be80c008bceeb6fb62fd1d450b5be5d0a4f).
> >
> > The aspeed-g5.dtsi I use is the same with the one in your link.
> >
> > I follow your suggestion and add the following to my dts but the
> SCU0C[8] is
> > still 1b'.
> >
> > &lpc_ctrl {
> >         status = "okay";
> > };
> >
> > Even I directly change the status of lpc_ctrl to 'okay'  in the
> > aspeed-g5.dtsi,  the SCU0C[8] is still 1b'.
> > lpc_ctrl: lpc-ctrl at 0 {
> >      compatible = "aspeed,ast2500-lpc-ctrl";
> >      reg = <0x0 0x80>;
> >      clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
> >      status = "okay";
> >  };
>
> Doing these two are equivalent. But it never hurts to try when things
> aren't working :)
>
> >
> > devmem 0x1e6e200c 32
> > 0xFFCDBF8B
>
> If you take a look a the driver, you will see this snippet:
>
> drivers/misc/aspeed-lpc-ctrl.c
>
> static long aspeed_lpc_ctrl_ioctl(struct file *file, unsigned int cmd,
>                 unsigned long param)
> {
>                 /*
>                  * Enable LPC FHW cycles. This is required for the host to
>                  * access the regions specified.
>                  */
>                 return regmap_update_bits(lpc_ctrl->regmap, HICR5,
>                                 HICR5_ENFWH | HICR5_ENL2H,
>                                 HICR5_ENFWH | HICR5_ENL2H);
>
>
> The driver is designed to only enable the bridge (ENL2H) when the
> configuration registers have been programmed by an ioctl() from
> userspace.
>
> This is to ensure the window is pointing at an area of memory that has
> been chosen by the system integrator, and not accidentally exposing
> some BMC RAM to the host. So the ioctl for programming the window will
> automatically enable the FWH and L2H bits (bits 10 and 8).
>
> On OpenPower systems, the tool that performs the ioctl is 'mboxd'. If
> you are using an OpenPower system, where the host firmware talks the
> mbox protocol (hostboot and skiboot do this), then you should run
> mboxd.
>
> If you're running on another platform, you could write a small utility
> to do this ioctl from userspace. I wrote one in Rust a few months ago,
> but you probably want to use C instead.
>
> Cheers,
>
> Joel
>
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