<div dir="ltr">Hi Joel,<div><br></div><div>Thanks for your response.</div><div><br></div><div>But I don't understand why 'SCU0C[8] = 1' is related with aspeed_lpc_ctrl_ioctl().</div><div><br></div><div>I don't see any code to write SCU0C register In the aspeed_lpc_ctrl_ioctl().</div><div><br></div><div>Update my finding. </div><div><br></div><div>I find the aspeed-lpc-ctrl driver can throw the below error message and 'return -ENODEV',</div><div>'Didn't find host pnor flash node'</div><div><br></div><div>After checking the my dts, it lacks of the 'flash' filed in the
<span style="font-size:small;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline">lpc_ctrl<span> </span></span>.</div><div><br></div><div>So I refer
<span style="font-size:small;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline">the aspeed-bmc-opp-zaius.dts</span> and add it into my dts.</div><div><div>&lpc_ctrl {</div><div> status = "okay";</div><div> memory-region = <&flash_memory>;</div><div> flash = <&spi1>;</div><div>};</div></div><div><br></div><div>And then the lpc
<span style="font-size:small;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline">aspeed-lpc-ctrl driver can be loaded successfully.</span></div><div><span style="font-size:small;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline">And the SCU0C[8] isn't set as 1b'.</span></div><div><span style="font-size:small;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline"><br></span></div><div><span style="font-size:small;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline">For my understanding, the 'spi1' indicates the system SPI connected into BIOS SPI flash.</span></div><div>I don't know why lpc_ctrl has to need the 'flash' field.</div><div><br></div><div>Thanks for your help.</div><div><br></div><div><div class="gmail_extra"><div class="gmail_quote">2018-06-06 17:01 GMT+08:00 Joel Stanley <span dir="ltr"><<a href="mailto:joel@jms.id.au" target="_blank">joel@jms.id.au</a>></span>:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Hello Henbin,<br>
<br>
tldr: you need to ensure mboxd has run so the aspeed-lpc-ctrl ioctl<br>
has been performed.<br>
<br>
See below for my explanation.<br>
<span class="gmail-"><br>
On 6 June 2018 at 14:32, Henbin Chang <<a href="mailto:henbinchang@gmail.com">henbinchang@gmail.com</a>> wrote:<br>
>> What kernel tree are you building/booting? Can you provide a link?<br>
>> Currently we've tied the LCLK to enabling LPC2AHB bridge:<br>
>><br>
>> <a href="https://github.com/openbmc/linux/blob/dev-4.13/arch/arm/boot/dts/aspeed-g5.dtsi#L302" rel="noreferrer" target="_blank">https://github.com/openbmc/<wbr>linux/blob/dev-4.13/arch/arm/<wbr>boot/dts/aspeed-g5.dtsi#L302</a><br>
>> You may need to add the following to your dts if you've developed your<br>
>> own:<br>
>> ```<br>
>> &lpc_ctrl {<br>
>> status = "okay";<br>
>> };<br>
><br>
</span><span class="gmail-">> I use dev-4.13 branch (the last commit is<br>
> aca92be80c008bceeb6fb62fd1d450<wbr>b5be5d0a4f).<br>
><br>
> The aspeed-g5.dtsi I use is the same with the one in your link.<br>
><br>
> I follow your suggestion and add the following to my dts but the SCU0C[8] is<br>
> still 1b'.<br>
><br>
> &lpc_ctrl {<br>
> status = "okay";<br>
> };<br>
><br>
> Even I directly change the status of lpc_ctrl to 'okay' in the<br>
> aspeed-g5.dtsi, the SCU0C[8] is still 1b'.<br>
> lpc_ctrl: lpc-ctrl@0 {<br>
> compatible = "aspeed,ast2500-lpc-ctrl";<br>
> reg = <0x0 0x80>;<br>
> clocks = <&syscon ASPEED_CLK_GATE_LCLK>;<br>
> status = "okay";<br>
> };<br>
<br>
</span>Doing these two are equivalent. But it never hurts to try when things<br>
aren't working :)<br>
<br>
><br>
> devmem 0x1e6e200c 32<br>
> 0xFFCDBF8B<br>
<br>
If you take a look a the driver, you will see this snippet:<br>
<br>
drivers/misc/aspeed-lpc-ctrl.c<br>
<br>
static long aspeed_lpc_ctrl_ioctl(struct file *file, unsigned int cmd,<br>
unsigned long param)<br>
{<br>
/*<br>
* Enable LPC FHW cycles. This is required for the host to<br>
* access the regions specified.<br>
*/<br>
return regmap_update_bits(lpc_ctrl-><wbr>regmap, HICR5,<br>
HICR5_ENFWH | HICR5_ENL2H,<br>
HICR5_ENFWH | HICR5_ENL2H);<br>
<br>
<br>
The driver is designed to only enable the bridge (ENL2H) when the<br>
configuration registers have been programmed by an ioctl() from<br>
userspace.<br>
<br>
This is to ensure the window is pointing at an area of memory that has<br>
been chosen by the system integrator, and not accidentally exposing<br>
some BMC RAM to the host. So the ioctl for programming the window will<br>
automatically enable the FWH and L2H bits (bits 10 and 8).<br>
<br>
On OpenPower systems, the tool that performs the ioctl is 'mboxd'. If<br>
you are using an OpenPower system, where the host firmware talks the<br>
mbox protocol (hostboot and skiboot do this), then you should run<br>
mboxd.<br>
<br>
If you're running on another platform, you could write a small utility<br>
to do this ioctl from userspace. I wrote one in Rust a few months ago,<br>
but you probably want to use C instead.<br>
<br>
Cheers,<br>
<br>
Joel<br>
</blockquote></div><br></div></div></div>