[PATCH linux dev-4.13 3/3] soc: aspeed-lpc-ctrl: Enable FWH cycles

Joel Stanley joel at jms.id.au
Fri Feb 9 15:38:32 AEDT 2018

On Fri, Feb 9, 2018 at 12:18 PM, Joel Stanley <joel at jms.id.au> wrote:
> On Thu, Feb 8, 2018 at 6:22 PM, Andrew Jeffery <andrew at aj.id.au> wrote:
>> On Thu, 2018-02-08 at 16:07 +1030, Joel Stanley wrote:
>>> +#define HICR5 0x0
>>> +#define HICR5_ENL2H  BIT(8)
>> Shouldn't we be setting this at the same time as HICR5_ENFWH below?
> In our testing we didn't require it.
> Lei, can you double check that the patch works from a power cycle
> without setting bit 8 in 0x1e789080?

Our testing was off. We discovered that bit 10 is always set (in this
case by u-boot, in platform.S), but we need to set bit 8.

I will send a v2.



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