[PATCH linux dev-4.17 2/2] mtd: spi-nor: fix spi register address for AST2400

[Cédric Le Goater]

On 08/16/2018 12:40 PM, Alexander Soldatov wrote:
> According to AST2400 datasheet v1.4 the SPI Flash Read Timing
> Setting register is at offset 0x14. There is no register at
> offset 0x94 (unlike FMC controller and AST2500).

The setting of the read timing register is not in mainline yet, 
so the patch won't apply. I will merge the fix in my patchset.



Thanks,

C. 


> 
> Cc: stable at vger.kernel.org
> Fixes: aad58eba7209 ("mtd: spi-nor: aspeed: optimize read mode")
> Signed-off-by: Alexander Soldatov <a.soldatov at yadro.com>
> ---
>  drivers/mtd/spi-nor/aspeed-smc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c
> index c9cd20f199d9..9ddf24b042f1 100644
> --- a/drivers/mtd/spi-nor/aspeed-smc.c
> +++ b/drivers/mtd/spi-nor/aspeed-smc.c
> @@ -71,7 +71,7 @@ static const struct aspeed_smc_info spi_2400_info = {
>  	.hastype = false,
>  	.we0 = 0,
>  	.ctl0 = 0x04,
> -	.timing = 0x94,
> +	.timing = 0x14,
>  	.set_4b = aspeed_smc_chip_set_4b_spi_2400,
>  	.optimize_read = aspeed_smc_optimize_read,
>  };
>