[PATCH linux dev-4.10 v2 11/11] aspeed: zaius: Disable GPIO bias via devicetree pinconf requests

[Andrew Jeffery]

On Sat, Apr 29, 2017, at 06:03, Xo Wang wrote:
> On Fri, Apr 28, 2017 at 12:10 AM, Andrew Jeffery <andrew at aj.id.au> wrote:
> > Signed-off-by: Andrew Jeffery <andrew at aj.id.au>
> > ---
> >  arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 16 ++++++++++++----
> >  arch/arm/mach-aspeed/aspeed.c              |  4 ----
> >  2 files changed, 12 insertions(+), 8 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
> > index acf7cc8d0e6d..b5c4c0fb2986 100644
> > --- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
> > +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
> > @@ -333,7 +333,19 @@
> >          */
> >  };
> >
> > +&pinctrl {
> > +       aspeed,external-nodes = <&gfx &lhc>;
> > +
> > +       pinctrl_gpioh_unbiased: gpioi_unbiased {
> > +               pins = "A8", "C7", "B7", "A7", "D7", "B6", "A6", "E7";
> 
> Out of curiosity, do you need to specify all eight pins affected by
> the "unbiased" register bit, or only the ones that you need for some
> functionality? In this case, only the first four pins are required for
> the 1-wire interfaces, but the whole port's pull-downs are controlled
> by one bit.

Yeah it's somewhat arbitrary. Any of these options will work. A downside
to specifying multiple pins is redundant writes (though they happen
once, at boot). The downside of specifying one pin is a broken
abstraction. Maybe your suggestion is best, that we only specify the
pins Zaius needs to configure, even if the result is all of bank H has
the bias disabled. Should I send a v3?

Andrew