[PATCH 2/3] aspeed/g5: helper SCU functions for configuring aspeed I2C
maxims at google.com
maxims at google.com
Wed Sep 28 03:43:33 AEST 2016
From: Maxim Sloyko <maxims at google.com>
---
arch/arm/include/asm/arch-aspeed/ast_scu.h | 6 +++
arch/arm/include/asm/arch-aspeed/regs-scu.h | 74 ++++++++++++++++-------------
arch/arm/mach-aspeed/ast-scu.c | 30 +++++++++++-
3 files changed, 75 insertions(+), 35 deletions(-)
diff --git a/arch/arm/include/asm/arch-aspeed/ast_scu.h b/arch/arm/include/asm/arch-aspeed/ast_scu.h
index d248416..80ebd6f 100644
--- a/arch/arm/include/asm/arch-aspeed/ast_scu.h
+++ b/arch/arm/include/asm/arch-aspeed/ast_scu.h
@@ -38,6 +38,7 @@ extern void ast_scu_get_who_init_dram(void);
extern u32 ast_get_clk_source(void);
extern u32 ast_get_h_pll_clk(void);
extern u32 ast_get_ahbclk(void);
+extern u32 ast_get_apbclk(void);
extern u32 ast_scu_get_vga_memsize(void);
@@ -45,4 +46,9 @@ extern void ast_scu_init_eth(u8 num);
extern void ast_scu_multi_func_eth(u8 num);
extern void ast_scu_multi_func_romcs(u8 num);
+/* Enable I2C controller and pins for a particular device.
+ * Device numbering starts at 1
+ */
+extern void ast_scu_enable_i2c(u8 num);
+
#endif
diff --git a/arch/arm/include/asm/arch-aspeed/regs-scu.h b/arch/arm/include/asm/arch-aspeed/regs-scu.h
index b89df82..92ce84a 100644
--- a/arch/arm/include/asm/arch-aspeed/regs-scu.h
+++ b/arch/arm/include/asm/arch-aspeed/regs-scu.h
@@ -10,8 +10,8 @@
* 1. 2012/12/29 Ryan Chen Create
*
********************************************************************************/
-#ifndef __AST_SCU_H
-#define __AST_SCU_H 1
+#ifndef __AST_REGS_SCU_H
+#define __AST_REGS_SCU_H 1
#include <asm/arch/aspeed.h>
@@ -830,49 +830,50 @@
/* AST_SCU_FUN_PIN_CTRL5 0x90 - Multi-function Pin Control#5 */
#define SCU_FUN_PIN_SPICS1 (0x1 << 31)
#define SCU_FUN_PIN_LPC_PLUS (0x1 << 30)
-#define SCU_FUC_PIN_USB20_HOST (0x1 << 29)
-#define SCU_FUC_PIN_USB11_PORT4 (0x1 << 28)
-#define SCU_FUC_PIN_I2C14 (0x1 << 27)
-#define SCU_FUC_PIN_I2C13 (0x1 << 26)
-#define SCU_FUC_PIN_I2C12 (0x1 << 25)
-#define SCU_FUC_PIN_I2C11 (0x1 << 24)
-#define SCU_FUC_PIN_I2C10 (0x1 << 23)
-#define SCU_FUC_PIN_I2C9 (0x1 << 22)
-#define SCU_FUC_PIN_I2C8 (0x1 << 21)
-#define SCU_FUC_PIN_I2C7 (0x1 << 20)
-#define SCU_FUC_PIN_I2C6 (0x1 << 19)
-#define SCU_FUC_PIN_I2C5 (0x1 << 18)
-#define SCU_FUC_PIN_I2C4 (0x1 << 17)
-#define SCU_FUC_PIN_I2C3 (0x1 << 16)
-#define SCU_FUC_PIN_MII2_RX_DWN_DIS (0x1 << 15)
-#define SCU_FUC_PIN_MII2_TX_DWN_DIS (0x1 << 14)
-#define SCU_FUC_PIN_MII1_RX_DWN_DIS (0x1 << 13)
-#define SCU_FUC_PIN_MII1_TX_DWN_DIS (0x1 << 12)
-
-#define SCU_FUC_PIN_MII2_TX_DRIV(x) (x << 10)
-#define SCU_FUC_PIN_MII2_TX_DRIV_MASK (0x3 << 10)
-#define SCU_FUC_PIN_MII1_TX_DRIV(x) (x << 8)
-#define SCU_FUC_PIN_MII1_TX_DRIV_MASK (0x3 << 8)
+#define SCU_FUN_PIN_USB20_HOST (0x1 << 29)
+#define SCU_FUN_PIN_USB11_PORT4 (0x1 << 28)
+#define SCU_FUN_PIN_I2C14 (0x1 << 27)
+#define SCU_FUN_PIN_I2C13 (0x1 << 26)
+#define SCU_FUN_PIN_I2C12 (0x1 << 25)
+#define SCU_FUN_PIN_I2C11 (0x1 << 24)
+#define SCU_FUN_PIN_I2C10 (0x1 << 23)
+#define SCU_FUN_PIN_I2C9 (0x1 << 22)
+#define SCU_FUN_PIN_I2C8 (0x1 << 21)
+#define SCU_FUN_PIN_I2C7 (0x1 << 20)
+#define SCU_FUN_PIN_I2C6 (0x1 << 19)
+#define SCU_FUN_PIN_I2C5 (0x1 << 18)
+#define SCU_FUN_PIN_I2C4 (0x1 << 17)
+#define SCU_FUN_PIN_I2C3 (0x1 << 16)
+#define SCU_FUN_PIN_I2C(n) (0x1 << (16 + (n) - 3))
+#define SCU_FUN_PIN_MII2_RX_DWN_DIS (0x1 << 15)
+#define SCU_FUN_PIN_MII2_TX_DWN_DIS (0x1 << 14)
+#define SCU_FUN_PIN_MII1_RX_DWN_DIS (0x1 << 13)
+#define SCU_FUN_PIN_MII1_TX_DWN_DIS (0x1 << 12)
+
+#define SCU_FUN_PIN_MII2_TX_DRIV(x) (x << 10)
+#define SCU_FUN_PIN_MII2_TX_DRIV_MASK (0x3 << 10)
+#define SCU_FUN_PIN_MII1_TX_DRIV(x) (x << 8)
+#define SCU_FUN_PIN_MII1_TX_DRIV_MASK (0x3 << 8)
#define MII_NORMAL_DRIV 0x0
#define MII_HIGH_DRIV 0x2
-#define SCU_FUC_PIN_UART6 (0x1 << 7)
-#define SCU_FUC_PIN_ROM_16BIT (0x1 << 6)
-#define SCU_FUC_PIN_DIGI_V_OUT(x) (x)
-#define SCU_FUC_PIN_DIGI_V_OUT_MASK (0x3)
+#define SCU_FUN_PIN_UART6 (0x1 << 7)
+#define SCU_FUN_PIN_ROM_16BIT (0x1 << 6)
+#define SCU_FUN_PIN_DIGI_V_OUT(x) (x)
+#define SCU_FUN_PIN_DIGI_V_OUT_MASK (0x3)
#define VIDEO_DISABLE 0x0
#define VIDEO_12BITS 0x1
#define VIDEO_24BITS 0x2
//#define VIDEO_DISABLE 0x3
-#define SCU_FUC_PIN_USB11_PORT2 (0x1 << 3)
-#define SCU_FUC_PIN_SD1_8BIT (0x1 << 3)
+#define SCU_FUN_PIN_USB11_PORT2 (0x1 << 3)
+#define SCU_FUN_PIN_SD1_8BIT (0x1 << 3)
-#define SCU_FUC_PIN_MAC1_MDIO (0x1 << 2)
-#define SCU_FUC_PIN_SD2 (0x1 << 1)
-#define SCU_FUC_PIN_SD1 (0x1 << 0)
+#define SCU_FUN_PIN_MAC1_MDIO (0x1 << 2)
+#define SCU_FUN_PIN_SD2 (0x1 << 1)
+#define SCU_FUN_PIN_SD1 (0x1 << 0)
/* AST_SCU_FUN_PIN_CTRL6 0x94 - Multi-function Pin Control#6*/
@@ -914,6 +915,11 @@
#define SCU_FUN_PIN_ROMA4 (0x1 << 18)
#define SCU_FUN_PIN_ROMA3 (0x1 << 17)
#define SCU_FUN_PIN_ROMA2 (0x1 << 16)
+/* AST2500 only */
+#define SCU_FUN_PIN_SDA2 (0x1 << 15)
+#define SCU_FUN_PIN_SCL2 (0x1 << 14)
+#define SCU_FUN_PIN_SDA1 (0x1 << 13)
+#define SCU_FUN_PIN_SCL1 (0x1 << 12)
/* AST_SCU_FUN_PIN_CTRL9 0xA8 - Multi-function Pin Control#9 */
#define SCU_FUN_PIN_ROMA21 (0x1 << 3)
diff --git a/arch/arm/mach-aspeed/ast-scu.c b/arch/arm/mach-aspeed/ast-scu.c
index 0cc0d67..1452b93 100644
--- a/arch/arm/mach-aspeed/ast-scu.c
+++ b/arch/arm/mach-aspeed/ast-scu.c
@@ -318,6 +318,14 @@ u32 ast_get_ahbclk(void)
#endif /* AST_SOC_G5 */
+u32 ast_get_apbclk(void)
+{
+ u32 h_pll = ast_get_h_pll_clk();
+ u32 apb_div = SCU_GET_PCLK_DIV(ast_scu_read(AST_SCU_CLK_SEL));
+ return h_pll / apb_div;
+}
+
+
void ast_scu_show_system_info(void)
{
@@ -394,7 +402,7 @@ void ast_scu_multi_func_eth(u8 num)
AST_SCU_FUN_PIN_CTRL1);
ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL5) |
- SCU_FUC_PIN_MAC1_MDIO,
+ SCU_FUN_PIN_MAC1_MDIO,
AST_SCU_FUN_PIN_CTRL5);
break;
@@ -496,3 +504,23 @@ void ast_scu_get_who_init_dram(void)
break;
}
}
+
+void ast_scu_enable_i2c(u8 num)
+{
+ /* Enable I2C Controllers */
+ clrbits_le32(AST_SCU_BASE + AST_SCU_RESET, SCU_RESET_I2C);
+
+ if (num < 3) {
+#ifdef AST_SOC_G5
+ if (num == 1) {
+ setbits_le32(AST_SCU_BASE + AST_SCU_FUN_PIN_CTRL8,
+ SCU_FUN_PIN_SDA1 | SCU_FUN_PIN_SCL1);
+ } else {
+ setbits_le32(AST_SCU_BASE + AST_SCU_FUN_PIN_CTRL8,
+ SCU_FUN_PIN_SDA2 | SCU_FUN_PIN_SCL2);
+ }
+#endif
+ } else {
+ setbits_le32(AST_SCU_BASE + AST_SCU_FUN_PIN_CTRL5, SCU_FUN_PIN_I2C(num));
+ }
+}
--
2.8.0.rc3.226.g39d4020
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