libflash questions mostly relating to P9 bringup

Xo Wang xow at
Sat Sep 24 11:41:26 AEST 2016

Hi folks,

I'm under the impression for P9 bringup we're sticking with BMC-side
MMIO to set up host PNOR access (as in what the host is booting from
over LPC). I see—and agree—that we're not gonna have MTD working by
the time we need to boot early machines:

What does libflash-based PNOR control look like? I mean the hacky way
we're gonna use for the next month. This is how I *think* it works.

booting the host:
1) the SMC SPI flash master auto-detects (?) how to read like the FMC
2) Swiss Army aspeed.c do_x_setup() enables LPC/AHB bridge to the SPI
flash window
Is that it? Doesn't involve MTD or pflash at all and it just works?

updating PNOR from BMC:
1) org.openbmc.control.Flash's update method calls op-flasher
2) org.openbmc.control.Flasher invokes libflash erase and program
3) libflash arch_flash_arm_io.h (?) and friends
  a. know how to talk to the flash controller (BMC_DIRECT)
  b. map AHB, GPIO, and SMC window from /dev/mem
  c. know the size of the host PNOR? (it looks hardcoded)

updating PNOR from host:
1) whatever calls pflash on host
2) host libflash powerpc_io.c and friends poke BMC registers over LPC
  a. write whatever LPC stuff that turns on iLPC2AHB, then use that to
set GPIO and SMC window to LPC for host access
  b. powerpc_io.c also overwrites the LPC/AHB bridge mapping (previous
set by BMC kernel) with its own desired config

Can somebody review that I got all this right? I saw some conflicting
information in

Other questions:
- what's the plan for "booting the host" and "updating PNOR from BMC?"
- is it worth extending the current libflash to read BMC & PNOR size,
window, etc from device tree?
- what does arch_flash_powerpc.c do? It looks like a whole other
access method with a host-side MTD device.


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