[PATCH 07/16] pinctrl-aspeed-g4: Add definition for GPIO pins J2 and

[Andrew Jeffery]

On Thu, 2016-09-15 at 15:35 -0500, Timothy Pearson wrote:
>  O2
> 
> This is required for Firestone to boot.

Just for future reference, on Firestone:

GPIOJ1 is BMC_CFAM_RESET_N
GPIOO2 is BMC_CP0_RESET_N

This looks good to me.

However, I was intending to implement all outstanding pins for the 2400
and 2500 today now that the Aspeed pinctrl core has been accepted
upstream. If you don't mind I'll just merge what you have done here
into those patches.

Cheers,

Andrew

> ---
>  drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c |   15 +++++++++++++--
>  1 file changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
> index e356619..610ab48 100644
> --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
> +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
> @@ -499,6 +499,9 @@ MS_PIN_DECL(E7, GPIOH7, ROMD15, RXD6);
>  
>  FUNC_GROUP_DECL(UART6, A8, C7, B7, A7, D7, B6, A6, E7);
>  
> +#define K5 74
> +SSSF_PIN_DECL(K5, GPIOJ2, SGPMO, SIG_DESC_SET(SCU84, 10));
> +
>  #define J3 75
>  SSSF_PIN_DECL(J3, GPIOJ3, SGPMI, SIG_DESC_SET(SCU84, 11));
>  
> @@ -727,10 +730,14 @@ SS_PIN_DECL(V6, GPIOO0, VPIG8);
>  SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9));
>  SS_PIN_DECL(Y5, GPIOO1, VPIG9);
>  
> +#define AA4 114
> +SIG_EXPR_LIST_DECL_SINGLE(VPIR0, VPI30, VPI30_DESC, SIG_DESC_SET(SCU88, 10));
> +SS_PIN_DECL(AA4, GPIOO2, VPIR0);
> +
>  FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, AA22, W5, Y4, AA3, AB2);
>  FUNC_GROUP_DECL(VPI24, T5, U3, V1, U4, V2, AA22, W5, Y4, AA3, AB2, V6, Y5);
> -FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, W4, Y3, AA22, W5, Y4, AA3,
> -		AB2);
> +FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, W4, Y3, AA4, AA22, W5, Y4,
> +		AA3, AB2);
>  
>  #define Y7 125
>  SIG_EXPR_LIST_DECL_SINGLE(GPIOP5, GPIOP5);
> @@ -1154,6 +1161,7 @@ static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = {
>  	ASPEED_PINCTRL_PIN(J20),
>  	ASPEED_PINCTRL_PIN(J21),
>  	ASPEED_PINCTRL_PIN(J3),
> +	ASPEED_PINCTRL_PIN(K5),
>  	ASPEED_PINCTRL_PIN(K18),
>  	ASPEED_PINCTRL_PIN(L22),
>  	ASPEED_PINCTRL_PIN(N21),
> @@ -1189,6 +1197,7 @@ static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = {
>  	ASPEED_PINCTRL_PIN(Y4),
>  	ASPEED_PINCTRL_PIN(Y5),
>  	ASPEED_PINCTRL_PIN(Y7),
> +	ASPEED_PINCTRL_PIN(AA4),
>  };
>  
>  static const struct aspeed_pin_group aspeed_g4_groups[] = {
> @@ -1231,6 +1240,7 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = {
>  	ASPEED_PINCTRL_GROUP(FLBUSY),
>  	ASPEED_PINCTRL_GROUP(FLWP),
>  	ASPEED_PINCTRL_GROUP(UART6),
> +	ASPEED_PINCTRL_GROUP(SGPMO),
>  	ASPEED_PINCTRL_GROUP(SGPMI),
>  	ASPEED_PINCTRL_GROUP(VGAHS),
>  	ASPEED_PINCTRL_GROUP(VGAVS),
> @@ -1341,6 +1351,7 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = {
>  	ASPEED_PINCTRL_FUNC(FLBUSY),
>  	ASPEED_PINCTRL_FUNC(FLWP),
>  	ASPEED_PINCTRL_FUNC(UART6),
> +	ASPEED_PINCTRL_FUNC(SGPMO),
>  	ASPEED_PINCTRL_FUNC(SGPMI),
>  	ASPEED_PINCTRL_FUNC(VGAHS),
>  	ASPEED_PINCTRL_FUNC(VGAVS),
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