[PATCH linux] pinctrl-aspeed-g5: Never set SCU90[6]

[Andrew Jeffery]

On Mon, 2016-10-31 at 17:01 +1030, Joel Stanley wrote:
> Hi Andrew,
> 
> Thanks for finding a fix so quickly.
> 
> On Mon, Oct 31, 2016 at 4:41 PM, Andrew Jeffery <andrew at aj.id.au> wrote:
> > 
> > The description of SCU90[6] from the datasheet: 'Reserved, must keep at
> > value ”0”'.
> > 
> > Switch from the bit-flipping macro to explicitly configuring
> > .enable = .disable = 0.
> > 
> > If a pin depending on SCU90[6] is requested for GPIO, the export will
> > succeed but changes to the GPIO's value fail to stick. With the fix the
> > value can be toggled as expected. The patch has been tested on an
> > AST2500 EVB.
> I couldn't follow what the issue was and how you fixed it, so I've
> rewritten it in laymans terms. Let me know what you think:
> 
> If a pin depending on bit 6 in SCU90 is requested for GPIO, the export
> will succeed but changes to the GPIO's value will not be accepted by
> the hardware. This is because pinmux has misconfigured the SCU by
> writing 1 to the reserved bit.
> 
> The description of SCU90[6] from the datasheet is 'Reserved, must keep
> at value ”0”'. The fix is to switch pinmux from the bit-flipping macro
> to explicitly configuring the .enable and .disable values to zero.
> 
> The patch has been tested on an AST2500 EVB.
> 

This flows a lot better. I'll send a v2.

Thanks,

Andrew

> Cheers,
> 
> Joel
> 
> > 
> > 
> > Reported-by: Uma Yadlapati <yadlapat at us.ibm.com>
> > Signed-off-by: Andrew Jeffery <andrew at aj.id.au>
> > ---
> >  drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> > index 481e836d12e5..9a3139c13ffc 100644
> > --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> > +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> > @@ -26,7 +26,7 @@
> > 
> >  #define ASPEED_G5_NR_PINS 232
> > 
> > -#define COND1          SIG_DESC_BIT(SCU90, 6, 0)
> > +#define COND1          { SCU90, BIT(6), 0, 0 }
> >  #define COND2          { SCU94, GENMASK(1, 0), 0, 0 }
> > 
> >  #define LHCR0          SIG_DESC_TO_REG(ASPEED_IP_LPC, 0xA0)
> > --
> > 2.7.4
> > 
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