[PATCH linux] pinctrl-aspeed-g5: Never set SCU90[6]

[Andrew Jeffery]

On Mon, 2016-10-31 at 07:31 +0100, Cédric Le Goater wrote:
> On 10/31/2016 07:11 AM, Andrew Jeffery wrote:
> > 
> > The description of SCU90[6] from the datasheet: 'Reserved, must keep at
> > value ”0”'.
> > 
> > Switch from the bit-flipping macro to explicitly configuring
> > .enable = .disable = 0.
> > 
> > If a pin depending on SCU90[6] is requested for GPIO, the export will
> > succeed but changes to the GPIO's value fail to stick. With the fix the
> > value can be toggled as expected. The patch has been tested on an
> > AST2500 EVB.
> That is an important condition for SP1 also.

Indeed, though in this case the mux is not affected because SPI1 is the
highest priority function for the relevant pins, and SCU90[6]'s default
value is zero. Therefore it won't ever have been (wrongly) toggled by
this bug in the pinmux driver configuration.

> Could that have an impact on 
> the spi1debug setting in the witherspoon DTS ? 

No: The need to configure spi1debug in the devicetree is purely driven
by the value in bits 12 and 13 of the strap register. If we want to use
some other configuration in the devicetree, e.g. spi1master, then we
need to change the strapping register in some way (e.g. hardware or u-
boot). However, Kun Yi was looking at whether we can make this more
flexible.

> Is it still needed ? 

Yes, per the above.

> 
> C.
> 
> > 
> > Reported-by: Uma Yadlapati <yadlapat at us.ibm.com>
> > Signed-off-by: Andrew Jeffery <andrew at aj.id.au>
> > ---
> >  drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> > index 481e836d12e5..9a3139c13ffc 100644
> > --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> > +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> > @@ -26,7 +26,7 @@
> >  
> >  #define ASPEED_G5_NR_PINS 232
> >  
> > -#define COND1		SIG_DESC_BIT(SCU90, 6, 0)
> > +#define COND1		{ SCU90, BIT(6), 0, 0 }
> >  #define COND2		{ SCU94, GENMASK(1, 0), 0, 0 }
> >  
> >  #define LHCR0		SIG_DESC_TO_REG(ASPEED_IP_LPC, 0xA0)
> > 
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