回信:Re:_回信:Re:_[PATCH_linux]_Add_debounce_for_power_button,_pull_down_gpioQ7_to_unlock_identify_LED
ken.th.liu at foxconn.com
ken.th.liu at foxconn.com
Tue May 17 19:55:17 AEST 2016
<DIV style="FONT-SIZE: 10pt; FONT-FAMILY: Microsoft Sans Serif">Hi Joel</DIV>
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<DIV style="FONT-SIZE: 10pt; FONT-FAMILY: Microsoft Sans Serif">OK</DIV>
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<DIV style="FONT-SIZE: 10pt; FONT-FAMILY: Microsoft Sans Serif">So you mean for the debounce setting.</DIV>
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<DIV style="FONT-SIZE: 10pt; FONT-FAMILY: Microsoft Sans Serif">I have to make a new pull request on /openbmc/linux with detail commit in github?</DIV>
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<DIV style="FONT-SIZE: 10pt; FONT-FAMILY: Microsoft Sans Serif">Thanks.<BR><BR>========================================<BR><BR>劉亭宏 Ken Liu<BR>Foxconn / Hon Hai Precision Ind. Co., Ltd.<BR>CESBG - Cloud Enterprise Solution Business Group<BR>SRD1<BR>Firmware Development Department<BR>TEL: +886-2-2268-3466 <BR>Ext. : 511 + 2704 (虎躍廠) <BR>Engineer (BMC Firmware)<BR>E-mail : ken.th.liu at foxconn.com<BR>(Ken T.H. Liu/CES/SUPERNOTES)<BR>2, Zihyou St., TU-CHENG, New TAIPEI City, 23644, Taiwan, R.O.C<BR><BR>========================================</DIV>
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<LABEL style="COLOR: #cc0099">— 回信者 ken.th.liu at mail.foxconn.com 於 2016/5/17 下午 05:53:07 —</LABEL><BR><BR>
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<TD style="COLOR: #0000ff" width=220>joel.stan at gmail.com</TD>
<TD style="COLOR: #0000ff" width=50 align=right>To： </TD>
<TD style="BORDER-TOP: 2px ridge; BORDER-RIGHT: 2px ridge; BORDER-BOTTOM: 2px ridge; BORDER-LEFT: 2px ridge" width=1000 noWrap>ken.th.liu at mail.foxconn.com</TD></TR>
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<TD style="COLOR: #0000ff" width=50 align=right>Cc： </TD>
<TD style="BORDER-TOP: 2px ridge; BORDER-RIGHT: 2px ridge; BORDER-BOTTOM: 2px ridge; BORDER-LEFT: 2px ridge" width=1000 noWrap>anoo at us.ibm.com,openbmc-patches at stwcx.xyz,openbmc at lists.ozlabs.org,sam.wc.su at foxconn.com,arvin.yh.yen at mail.foxconn.com,ken.sk.lai at mail.foxconn.com,andrew.cl.lin at mail.foxconn.com,john.hc.wang at mail.foxconn.com</TD></TR>
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<TD style="COLOR: #0000ff" width=220>2016/5/17 下午 03:49:07</TD>
<TD style="COLOR: #0000ff" width=50 align=right>主旨： </TD>
<TD style="BORDER-TOP: 2px ridge; BORDER-RIGHT: 2px ridge; BORDER-BOTTOM: 2px ridge; BORDER-LEFT: 2px ridge" width=1000 noWrap>Re:_回信:Re:_[PATCH_linux]_Add_debounce_for_power_ button,_pull_down_gpioQ7_to_unlock_identify_LED</TD></TR></TBODY></TABLE><BR></DIV>Hello Ken and Adriana,<BR><BR>It seems you both missed the email sent by Andrew on Friday:<BR><BR> https://lists.ozlabs.org/pipermail/openbmc/2016-May/003078.html<BR><BR>He also had some feedback for your patch.<BR><BR>I have some suggestions below that you can follow to help us proceed.<BR><BR>>> > > + writel(0x00001080, AST_IO(AST_BASE_GPIO | 0x84));<BR>>> > We have a GPIO driver that handles setting this register.<BR>><BR>> Agreed - superficially it looks like we should be doing this in e.g.<BR>> bin/Barreleye.py in the skeleton repo.<BR>><BR>> So looking there, R4 was previously described:<BR>><BR>> GPIO_CONFIG['HEART_BEAT'] = { 'gpio_pin': 'R4', 'direction':<BR>> 'out' }<BR>><BR>> But was removed by Adriana in skeleton's "9c75104b Implement new LED<BR>> driver" commit. Presumably this should've taken care of the<BR>> configuration of R4.<BR>><BR><BR>Are you aware that the identify LED is controlled by the gpio-leds<BR>driver in the kernel? Was this working?<BR>.<BR>You can see the configuration of this in the device tree<BR>arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts:<BR><BR> leds {<BR> compatible = "gpio-leds";<BR><BR> heartbeat {<BR> # GPIO R4, BMC_HEARTBRAT_LED_N<BR> gpios = <&gpio 140 GPIO_ACTIVE_HIGH>;<BR> };<BR> identify {<BR> # GPIO H2, BMC_SYS_PWROK_IDLED_N<BR> gpios = <&gpio 58 GPIO_ACTIVE_LOW>;<BR> };<BR> beep {<BR> # GPIO N7, BMC_BEEP<BR> gpios = <&gpio 111 GPIO_ACTIVE_HIGH>;<BR> };<BR> };<BR><BR><BR>> The register write is also configuring GPIOQ7 as output, but I can't<BR>> find mention of it in the skeleton history.<BR><BR>>> > > - writel(0x0031FFAF, AST_IO(AST_BASE_GPIO | 0x80));<BR>>> > > + writel(0x0031FF2F, AST_IO(AST_BASE_GPIO | 0x80));<BR>><BR>> So here we're bringing Q7 low. Can we deal with it as mentioned above?<BR><BR>As Andrew observed you are setting Q7 as an otuput and bringing it<BR>low. It is BMC_READY_N, which makes sense.<BR><BR>However, this can be and should be done in skeleton/bin/Barreleye.py.<BR><BR>Norm, as a policy, should we do this when the BMC userspace is up and ready?<BR><BR>>> > > + writel(0x00000001, AST_IO(AST_BASE_GPIO | 0x48));<BR>>> > > + writel(0x00000001, AST_IO(AST_BASE_GPIO | 0x4C));<BR>>> > > + writel(0x00075300, AST_IO(AST_BASE_GPIO | 0x58));<BR>><BR>> Right, so these registers configure debounce. I'm not sure why we<BR>> chose timer 3, but regardless, my understanding is that debounce cannot<BR>> be configured from userspace via sysfs.<BR><BR>Andrew points out that we need to do denounce configuration where you<BR>have, for now.<BR><BR>Please re-submit this part of the patch with a commit message about<BR>what GPIOs are being configured and why.<BR><BR>You could write something like:<BR><BR>"This configures GPIOE0, which is BMC_PWBTN_IN_N, to be debounced. It<BR>uses timer 3 for 480000 cycles, which with a pclk of 24MHz is 20<BR>milliseconds."<BR><BR>Cheers,<BR><BR>Joel<BR><BR>On Tue, May 17, 2016 at 12:35 PM, <ken.th.liu at foxconn.com> wrote:<BR>><BR>> Hi Adri<BR>><BR>> Response as below.<BR>> Hi Ken,<BR>><BR>> Could you reply to Joel if you have any questions about his comments or make a new pull request so that the change can be merged? Specifically is provide more info regarding the changes, I'm copying the comments here. Thanks.<BR>><BR>><BR>> >> From: Ken <ken.sk.lai at mail.foxconn.com><BR>> > We need to include a description of why this change is being made.<BR>> > What does it fix? Why does the previous behaviour need to be modified?<BR>><BR>> It's fix when power on, the identify led can not be controlled.<BR>><BR>> And power button issue.<BR>><BR>><BR>><BR>> >> + writel(0x00001080, AST_IO(AST_BASE_GPIO | 0x84));<BR>> > We have a GPIO driver that handles setting this register.<BR>><BR>> OK. We can move the code to skeleton.<BR>><BR>><BR>><BR>> The GPIO is for unlock Identify LED by GPIOQ7 when power on.<BR>><BR>><BR>> >> + writel(0x010FFFFF, AST_IO(AST_BASE_SCU | 0xA8));<BR>> > Can you explain each of these you're setting each of these bits?<BR>><BR>> It's a long story, please check the attachment mail history.<BR>><BR>><BR>><BR>> To conclude, to avoid the debounce pulse for power button interrupt.<BR>><BR>><BR>><BR>><BR>><BR>> From: Joel Stanley <joel at jms.id.au><BR>> To: OpenBMC Patches <openbmc-patches at stwcx.xyz>, ken.th.liu at foxconn.com<BR>> Cc: OpenBMC Maillist <openbmc at lists.ozlabs.org><BR>> Date: 05/12/2016 02:11 AM<BR>> Subject: Re: [PATCH linux] Add debounce for power button, pull down gpioQ7 to unlock identify LED<BR>> Sent by: "openbmc" <openbmc-bounces+anoo=us.ibm.com at lists.ozlabs.org><BR>> ________________________________<BR>><BR>><BR>><BR>> ping<BR>><BR>> On Mon, May 2, 2016 at 11:12 AM, Joel Stanley <joel at jms.id.au> wrote:<BR>> > On Fri, Apr 29, 2016 at 3:10 PM, OpenBMC Patches<BR>> > <openbmc-patches at stwcx.xyz> wrote:<BR>> >> From: Ken <ken.sk.lai at mail.foxconn.com><BR>> >><BR>> ><BR>> > We need to include a description of why this change is being made.<BR>> > What does it fix? Why does the previous behaviour need to be modified?<BR>> ><BR>> >> ---<BR>> >> arch/arm/mach-aspeed/aspeed.c | 8 ++++++--<BR>> >> 1 file changed, 6 insertions(+), 2 deletions(-)<BR>> >> mode change 100644 => 100755 arch/arm/mach-aspeed/aspeed.c<BR>> >><BR>> >> diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c<BR>> >> old mode 100644<BR>> >> new mode 100755<BR>> >> index 594a781..fa5d467<BR>> >> --- a/arch/arm/mach-aspeed/aspeed.c<BR>> >> +++ b/arch/arm/mach-aspeed/aspeed.c<BR>> >> @@ -138,9 +138,10 @@ static void __init do_barreleye_setup(void)<BR>> >> /* GPIO setup */<BR>> >> writel(0x9E82FCE7, AST_IO(AST_BASE_GPIO | 0x00));<BR>> >> writel(0x0370E677, AST_IO(AST_BASE_GPIO | 0x04));<BR>> >> -<BR>> >> + writel(0x00001080, AST_IO(AST_BASE_GPIO | 0x84));<BR>> ><BR>> > We have a GPIO driver that handles setting this register.<BR>> ><BR>> >> /* SCU setup */<BR>> >> writel(0x01C00000, AST_IO(AST_BASE_SCU | 0x88));<BR>> >> + writel(0x010FFFFF, AST_IO(AST_BASE_SCU | 0xA8));<BR>> ><BR>> > Can you explain each of these you're setting each of these bits?<BR>> ><BR>> >> /*<BR>> >> * Do read/modify/write on power gpio to prevent resetting power on<BR>> >> @@ -150,7 +151,10 @@ static void __init do_barreleye_setup(void)<BR>> >> reg |= 0xCFC8F7FD;<BR>> >> writel(reg, AST_IO(AST_BASE_GPIO | 0x20));<BR>> >> writel(0xC738F20A, AST_IO(AST_BASE_GPIO | 0x24));<BR>> >> - writel(0x0031FFAF, AST_IO(AST_BASE_GPIO | 0x80));<BR>> >> + writel(0x0031FF2F, AST_IO(AST_BASE_GPIO | 0x80));<BR>> >> + writel(0x00000001, AST_IO(AST_BASE_GPIO | 0x48));<BR>> >> + writel(0x00000001, AST_IO(AST_BASE_GPIO | 0x4C));<BR>> >> + writel(0x00075300, AST_IO(AST_BASE_GPIO | 0x58));<BR>> ><BR>> > As above; we have a GPIO driver that handles setting this register.<BR>> > Changing these states needs to be done from userspace. See<BR>> > https://github.com/openbmc/skeleton/blob/master/bin/Barreleye.py#L531<BR>
<DIV style="FONT-SIZE: 10pt; FONT-FAMILY: Microsoft Sans Serif"><BR>mail from ip-->10.38.3.183<BR>mail from pc-->KEN<BR>Version: Super Notes 1.6.5.9B</DIV>
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