[PATCH 1/2] pinctrl/aspeed: Add GPIOR to g4 pinmux
Andrew Jeffery
andrew at aj.id.au
Thu Aug 11 11:40:28 AEST 2016
On Wed, 2016-08-10 at 18:51 +0930, Joel Stanley wrote:
> Signed-off-by: Joel Stanley <joel at jms.id.au>
> ---
> drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 81 ++++++++++++++++++++++++++++--
> 1 file changed, 78 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
> index d36e14892d4e..96952bf33b9f 100644
> --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
> +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
> @@ -585,6 +585,71 @@ SIG_EXPR_LIST_DECL(ROMCS1, SIG_EXPR_PTR(ROMCS1, ROM8),
> SIG_EXPR_PTR(ROMCS1, ROM16S));
> MS_PIN_DECL_(V20, SIG_EXPR_LIST_PTR(ROMCS1), SIG_EXPR_LIST_PTR(GPIOR0));
>
> +#define W21 137
> +#define W21_DESC SIG_DESC_SET(SCU88, 25)
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOR1, GPIOR1);
> +SIG_EXPR_DECL(ROMCS2, ROM8, W21_DESC);
> +SIG_EXPR_DECL(ROMCS2, ROM16, W21_DESC);
> +SIG_EXPR_DECL(ROMCS2, ROM16S, W21_DESC);
> +SIG_EXPR_LIST_DECL(ROMCS2, SIG_EXPR_PTR(ROMCS2, ROM8),
> + SIG_EXPR_PTR(ROMCS2, ROM16),
> + SIG_EXPR_PTR(ROMCS2, ROM16S));
> +MS_PIN_DECL_(W21, SIG_EXPR_LIST_PTR(ROMCS2), SIG_EXPR_LIST_PTR(GPIOR1));
I'm thinking we should separate out muxing of the chip selects from
enabling the optional ROM signals. We need to hash that out before I
resend the patches upstream.
> +
> +#define Y22 138
> +#define Y22_DESC SIG_DESC_SET(SCU88, 26)
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOR2, GPIOR2);
> +SIG_EXPR_DECL(ROMCS3, ROM8, Y22_DESC);
> +SIG_EXPR_DECL(ROMCS3, ROM16, Y22_DESC);
> +SIG_EXPR_DECL(ROMCS3, ROM16S, Y22_DESC);
> +SIG_EXPR_LIST_DECL(ROMCS3, SIG_EXPR_PTR(ROMCS3, ROM8),
> + SIG_EXPR_PTR(ROMCS3, ROM16),
> + SIG_EXPR_PTR(ROMCS3, ROM16S));
> +MS_PIN_DECL_(Y22, SIG_EXPR_LIST_PTR(ROMCS3), SIG_EXPR_LIST_PTR(GPIOR2));
> +
> +#define U19 139
> +#define U19_DESC SIG_DESC_SET(SCU88, 27)
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOR3, GPIOR3);
> +SIG_EXPR_DECL(ROMCS4, ROM8, U19_DESC);
> +SIG_EXPR_DECL(ROMCS4, ROM16, U19_DESC);
> +SIG_EXPR_DECL(ROMCS4, ROM16S, U19_DESC);
> +SIG_EXPR_LIST_DECL(ROMCS4, SIG_EXPR_PTR(ROMCS4, ROM8),
> + SIG_EXPR_PTR(ROMCS4, ROM16),
> + SIG_EXPR_PTR(ROMCS4, ROM16S));
> +MS_PIN_DECL_(U19, SIG_EXPR_LIST_PTR(ROMCS4), SIG_EXPR_LIST_PTR(GPIOR3));
> +
> +#define V21 140
> +#define V21_DESC SIG_DESC_SET(SCU88, 28)
> +SIG_EXPR_DECL(ROMA24, ROM8, V21_DESC);
> +SIG_EXPR_DECL(ROMA24, ROM16, V21_DESC);
> +SIG_EXPR_DECL(ROMA24, ROM16S, V21_DESC);
Ah, bug here, the DECLs above should be:
SIG_EXPR_DECL(ROMA24, ROM8, V21_DESC, VPO_OFF_12);
SIG_EXPR_DECL(ROMA24, ROM16, V21_DESC, VPO_OFF_12);
SIG_EXPR_DECL(ROMA24, ROM16S, V21_DESC, VPO_OFF_12);
> +SIG_EXPR_LIST_DECL(ROMA24, SIG_EXPR_PTR(ROMA24, ROM8),
> + SIG_EXPR_PTR(ROMA24, ROM16),
> + SIG_EXPR_PTR(ROMA24, ROM16S));
> +SIG_EXPR_LIST_DECL_SINGLE(VPOR6, VPO24, V21_DESC, VPO_24_OFF);
> +MS_PIN_DECL(V21, GPIOR4, ROMA24, VPOR6);
> +
> +#define W22 141
> +#define W22_DESC SIG_DESC_SET(SCU88, 29)
> +SIG_EXPR_DECL(ROMA25, ROM8, W22_DESC);
> +SIG_EXPR_DECL(ROMA25, ROM16, W22_DESC);
> +SIG_EXPR_DECL(ROMA25, ROM16S, W22_DESC);
Similarly, these DECLs should be:
SIG_EXPR_DECL(ROMA25, ROM8, W22_DESC, VPO_OFF_12);
SIG_EXPR_DECL(ROMA25, ROM16, W22_DESC, VPO_OFF_12);
SIG_EXPR_DECL(ROMA25, ROM16S, W22_DESC, VPO_OFF_12);
Cheers,
Andrew
> +SIG_EXPR_LIST_DECL(ROMA25, SIG_EXPR_PTR(ROMA25, ROM8),
> + SIG_EXPR_PTR(ROMA25, ROM16),
> + SIG_EXPR_PTR(ROMA25, ROM16S));
> +SIG_EXPR_LIST_DECL_SINGLE(VPOR7, VPO24, W22_DESC, VPO_24_OFF);
> +MS_PIN_DECL(W22, GPIOR5, ROMA25, VPOR7);
> +
> +#define C6 142
> +SIG_EXPR_LIST_DECL_SINGLE(MDC1, MDIO1, SIG_DESC_SET(SCU88, 30));
> +SS_PIN_DECL(C6, GPIOR6, MDC1);
> +
> +#define A5 143
> +SIG_EXPR_LIST_DECL_SINGLE(MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31));
> +SS_PIN_DECL(A5, GPIOR7, MDIO1);
> +
> +FUNC_GROUP_DECL(MDIO1, C6, A5);
> +
> #define U21 144
> #define U21_DESC SIG_DESC_SET(SCU8C, 0)
> SIG_EXPR_DECL(ROMD4, ROM8, U21_DESC, VPOOFF0_DESC);
> @@ -681,11 +746,12 @@ SIG_EXPR_LIST_DECL(ROMA23, SIG_EXPR_PTR(ROMA23, ROM8),
> SIG_EXPR_LIST_DECL_SINGLE(VPOR5, VPO24, K18_DESC, VPO_24_OFF);
> MS_PIN_DECL(K18, GPIOS7, ROMA23, VPOR5);
>
> -FUNC_GROUP_DECL(ROM8, V20, U21, T19, V22, U20, R18, N21, L22, K18);
> +FUNC_GROUP_DECL(ROM8, V20, U21, T19, V22, U20, R18, N21, L22, K18, W21, Y22,
> + U19);
> FUNC_GROUP_DECL(ROM16, V20, U21, T19, V22, U20, R18, N21, L22, K18,
> - A8, C7, B7, A7, D7, B6, A6, E7);
> + A8, C7, B7, A7, D7, B6, A6, E7, W21, Y22, U19);
> FUNC_GROUP_DECL(VPO12, U21, T19, V22, U20);
> -FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18);
> +FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22);
>
> #define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0)
>
> @@ -792,6 +858,7 @@ static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = {
> ASPEED_PINCTRL_PIN(A2),
> ASPEED_PINCTRL_PIN(A3),
> ASPEED_PINCTRL_PIN(A4),
> + ASPEED_PINCTRL_PIN(A5),
> ASPEED_PINCTRL_PIN(A6),
> ASPEED_PINCTRL_PIN(A7),
> ASPEED_PINCTRL_PIN(A8),
> @@ -820,6 +887,7 @@ static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = {
> ASPEED_PINCTRL_PIN(C3),
> ASPEED_PINCTRL_PIN(C4),
> ASPEED_PINCTRL_PIN(C5),
> + ASPEED_PINCTRL_PIN(C6),
> ASPEED_PINCTRL_PIN(C7),
> ASPEED_PINCTRL_PIN(D1),
> ASPEED_PINCTRL_PIN(D11),
> @@ -861,6 +929,7 @@ static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = {
> ASPEED_PINCTRL_PIN(T5),
> ASPEED_PINCTRL_PIN(U1),
> ASPEED_PINCTRL_PIN(U18),
> + ASPEED_PINCTRL_PIN(U19),
> ASPEED_PINCTRL_PIN(U2),
> ASPEED_PINCTRL_PIN(U20),
> ASPEED_PINCTRL_PIN(U21),
> @@ -870,11 +939,15 @@ static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = {
> ASPEED_PINCTRL_PIN(V1),
> ASPEED_PINCTRL_PIN(V2),
> ASPEED_PINCTRL_PIN(V20),
> + ASPEED_PINCTRL_PIN(V21),
> ASPEED_PINCTRL_PIN(V22),
> ASPEED_PINCTRL_PIN(V6),
> ASPEED_PINCTRL_PIN(W1),
> + ASPEED_PINCTRL_PIN(W21),
> + ASPEED_PINCTRL_PIN(W22),
> ASPEED_PINCTRL_PIN(W4),
> ASPEED_PINCTRL_PIN(W5),
> + ASPEED_PINCTRL_PIN(Y22),
> ASPEED_PINCTRL_PIN(Y3),
> ASPEED_PINCTRL_PIN(Y4),
> ASPEED_PINCTRL_PIN(Y5),
> @@ -952,6 +1025,7 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = {
> ASPEED_PINCTRL_GROUP(VPO24),
> ASPEED_PINCTRL_GROUP(RGMII1),
> ASPEED_PINCTRL_GROUP(RMII1),
> + ASPEED_PINCTRL_GROUP(MDIO1),
> };
>
> static const struct aspeed_pin_function aspeed_g4_functions[] = {
> @@ -1022,6 +1096,7 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = {
> ASPEED_PINCTRL_FUNC(VPO24),
> ASPEED_PINCTRL_FUNC(RGMII1),
> ASPEED_PINCTRL_FUNC(RMII1),
> + ASPEED_PINCTRL_FUNC(MDIO1),
> };
>
> static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = {
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