AW: Re: __setup_cpu_be problem

[Benjamin Herrenschmidt]

On Wed, 2006-02-15 at 07:11 -0500, Jimi Xenidis wrote:
> On Feb 15, 2006, at 6:30 AM, Paul Mackerras wrote:
> 
> > Jimi Xenidis writes:
> >
> >> Are thinking of using Large PAges in IO space? Cuz I don't think you
> >> can.
> >
> > Why not?
> 
>  From the 970 User manual:
>    To avoid accidental large/small page translation aliasing, the  
> 970FX implements a HID4 bit (HID4[61]) to
>    disable the large page facility and does not permit cache  
> inhibited accesses to an address in a large page.
> 
> I'm not 100% but I believe this effects P4, and maybe even P5.
> WRT Cell, I believe the BPA_Map can be mapped with large pages but  
> I'm not sure about "real" devices.

AS 2.03 lifts this limitation, and from GS DD2.1 onward, L=1 can be
cache inhibited (this is a requirement for the kernel to be able to use
64k HW pages btw). I think Cell works that way too but that remains to
be confirmed.

Ben.