[PATCH] ppc64: iMac G5 cpufreq support

Benjamin Herrenschmidt benh at kernel.crashing.org
Sun Sep 25 08:05:27 EST 2005

> Comment is bogus (the low 16 bits _do_ have a defined
> function; the high 16 bits are the high 16 bits of the
> SCOM address; the low 7 bits of the 23-bit SCOM address
> are always zero and not implemented in this register;
> what you are _actually_ doing here is passing in the
> serial SCOM address and the parity bit, and shifting it
> and clearing out the parity bit so it is the right format
> for the SCOMC register).

Yah, I know what I'm doing thanks :) The comment is a bit
misleading indeed. It should read something like clear out
the low 8 bits of the address (including parity) as they
aren't supported by the SCOMC and always zero.

> 	mtspr	SPRN_SCOMC,r3
> 	isync
> 	mfspr	r3,SPRN_SCOMD
> 	mfspr	r0,SPRN_SCOMC

You just removed a few sync's...

> Instead:
> 	mtspr	SPRN_SCOMD,r4      /* write data */
> 	isync
> 	mtspr	SPRN_SCOMC,r3      /* write command */
> 	isync
> 	mfspr	3,SPRN_SCOMC

Here; you also just changed a few isync's ... oh well, I'll have
a look. I did the sync based on apple stuff, I suspect a sync before
would still be usedful to make sure pending memory accesses are
completed, not specifically for the frequency change, but in general
as the SCOM can be used to manipulate the L2 cache among others and
I may use it to put the cache in direct mode for flushing one of
these days.


More information about the Linuxppc64-dev mailing list