[PATCH] ppc64: iMac G5 cpufreq support

[Segher Boessenkool]

> +_GLOBAL(scom970_read)
> +	/* interrupts off */
> +	mfmsr	r4
> +	ori	r0,r4,MSR_EE
> +	xori	r0,r0,MSR_EE
> +	mtmsrd	r0,1
> +
> +	/* rotate address 8 bits left, mask out low 16 bits as they
> +	 * aren't implemented on current CPUs and must be 0'd,

Comment is bogus (the low 16 bits _do_ have a defined
function; the high 16 bits are the high 16 bits of the
SCOM address; the low 7 bits of the 23-bit SCOM address
are always zero and not implemented in this register;
what you are _actually_ doing here is passing in the
serial SCOM address and the parity bit, and shifting it
and clearing out the parity bit so it is the right format
for the SCOMC register).

> +	 * and finally or in RW bit
> +	 */
> +	rlwinm	r3,r3,8,0,15
> +	ori	r3,r3,0x8000
> +
> +	/* do the actual scom read */
> +	sync
> +	mtspr	SPRN_SCOMC,r3
> +	isync
> +	mfspr	r3,SPRN_SCOMD
> +	mfspr	r0,SPRN_SCOMC
> +	sync
> +	isync

Instead:

	mtspr	SPRN_SCOMC,r3
	isync
	mfspr	r3,SPRN_SCOMD
	mfspr	r0,SPRN_SCOMC


> +_GLOBAL(scom970_write)

[snip]

> +	mtspr	SPRN_SCOMD,r4      /* write data */
> +	mtspr	SPRN_SCOMC,r3      /* write command */
> +	sync
> +	isync
> +	mfspr	3,SPRN_SCOMC

Instead:
	mtspr	SPRN_SCOMD,r4      /* write data */
	isync
	mtspr	SPRN_SCOMC,r3      /* write command */
	isync
	mfspr	3,SPRN_SCOMC


Cheers,


Segher