Invert sense of SLB class bit

[Paul Mackerras]

linas writes:

> Antonb had been talking about something like this more than a year 
> ago ... as there was code added to not flush the 0xc segment.  
> Did that code not work? Or did it get broken? Or was it never 
> submitted upstream?

No, this is entirely different.  POWER5 creates ERAT entries for pages
which are accessed in real mode (these are created automatically by
the hardware as needed).  In other words, *all* accesses go through
the ERAT, there isn't a bypass for real mode.  The real-mode ERAT
entries are created with C=0, so by using C=0 for user mappings we
were blowing away all the real-mode entries on every context switch.

Paul.